公开(公告)号：US08796664B2

公开(公告)日：2014-08-05

申请号：US13685654

申请日：2012-11-26

申请人： Wen-Hui Duan ,  Yuan-Chang Li ,  Peng-Cheng Chen ,  Jian Wu ,  Bing-Lin Gu

发明人： Wen-Hui Duan ,  Yuan-Chang Li ,  Peng-Cheng Chen ,  Jian Wu ,  Bing-Lin Gu

IPC分类号： H01L29/06 ,  C01B31/04

CPC分类号： H01L29/1606 ,  B32B9/005 ,  B32B9/007 ,  B32B2255/205 ,  B32B2307/308 ,  B32B2457/00 ,  B82Y99/00 ,  H01L29/165 ,  Y10S977/734

摘要： A graphene-based composite structure is disclosed. The graphene-based composite structure includes a graphene layer, a transition metal layer, and a substrate. The graphene layer, transition metal layer, and substrate are stacked together in series to form a sandwich structure. The graphene layer and the transition metal layer are coupled by d-p orbitals hybridization. The transition metal layer and the substrate are also coupled by d-p orbitals hybridization. A method for making graphene-based composite structure is also disclosed.

摘要翻译： 公开了一种基于石墨烯的复合结构。 基于石墨烯的复合结构包括石墨烯层，过渡金属层和基底。 将石墨烯层，过渡金属层和基板串联堆叠以形成夹层结构。 石墨烯层和过渡金属层通过d-p轨道杂交耦合。 过渡金属层和底物也通过d-p轨道杂交耦合。 还公开了一种制备基于石墨烯的复合结构的方法。

公开(公告)号：US20230014869A1

公开(公告)日：2023-01-19

申请号：US17943113

申请日：2022-09-12

申请人： Horia C. Simionescu ,  Rohitkumar Makhija ,  Peng-Cheng Chen ,  Jung Sheng Hoei

发明人： Horia C. Simionescu ,  Rohitkumar Makhija ,  Peng-Cheng Chen ,  Jung Sheng Hoei

IPC分类号： G06F3/06

摘要： A method can include receiving, by a first controller component of a memory sub-system, a read operation, responsive to receiving the read operation, interrupting, by the first controller component, one or more program operations being performed by the memory sub-system, receiving, by the first controller component, a control sequence from a second controller component, wherein the control sequence is based on context data associated with the interrupted one or more program operations, and performing, by the first controller component, the control sequence by copying data of the interrupted one or more program operations from a first memory location to a second memory location of a memory component associated with the memory sub-system, and performing the read operation.

公开(公告)号：US20050091052A1

公开(公告)日：2005-04-28

申请号：US10758533

申请日：2004-01-16

申请人： Yuh-Chin Chang ,  Peng-Cheng Chen ,  Hui-Ya Chou ,  Hong-Tsan Lee

发明人： Yuh-Chin Chang ,  Peng-Cheng Chen ,  Hui-Ya Chou ,  Hong-Tsan Lee

IPC分类号： G10L19/02 ,  G10L19/14 ,  H04N9/802

CPC分类号： G10L19/24

摘要： A variable frequency decoding apparatus operable in a portable audio device that can improve the power management is disclosed. The above apparatus has a decoder and a clock generator that provides the system clock for the decoder. When a bit stream representing audio compressed data is received, the decoder simultaneously provides the audio information embedded in the audio compressed data such as the bit rate and the sampling frequency of the data frame to the clock generator, and then the clock generator adjusts the clock signals; which are used by the decoder to restore to the original PCM format, to match the audio information embedded in the data frame. This audio signal compression technique can prevent possible output delay and reduce power consumption as compared with the conventional way that used a fixed sys clock.

摘要翻译： 公开了一种在可改善电源管理的便携式音频设备中可操作的可变频率解码装置。 上述装置具有提供解码器的系统时钟的解码器和时钟发生器。 当接收到表示音频压缩数据的比特流时，解码器同时将音频压缩数据中嵌入的音频信息（例如数据帧的比特率和采样频率）提供给时钟发生器，然后时钟发生器调整时钟 信号; 其被解码器使用以恢复到原始PCM格式，以匹配嵌入在数据帧中的音频信息。 与使用固定系统时钟的常规方式相比，该音频信号压缩技术可以防止可能的输出延迟并降低功耗。

公开(公告)号：US20050078216A1

公开(公告)日：2005-04-14

申请号：US10758532

申请日：2004-01-16

申请人： Yuh-Chin Chang ,  Hui-Ya Chou ,  Hong-Tsan Lee ,  Peng-Cheng Chen

发明人： Yuh-Chin Chang ,  Hui-Ya Chou ,  Hong-Tsan Lee ,  Peng-Cheng Chen

IPC分类号： G10L19/00 ,  G11B15/00 ,  H04N7/00 ,  H04N7/173 ,  H04N11/00

CPC分类号： G10L19/005

摘要： A method of improving performance and power utilization of portable a CD player with an electronic anti-shock system (EASS) is disclosed. When PCM signals are received by the EASS, the audio signals are compressed with a high compression rate algorithm and saved in a temporary memory, and later when the audio data are read out from the temporary memory, the audio data are decoded with the same audio compression algorithm to restore to the original PCM format, thus a data buffering is created between the reading of data and the playback of sound. A high compression rate algorithm can increase the utilization of DRAM memory and lengthen the buffering time considerably. The present invention has incorporated an audio compression algorithm having high compression rate in the EASS to attain the most desirable balance point between audio performance, power management, and costs.

摘要翻译： 公开了一种提高具有电子防冲击系统（EASS）的便携式CD播放机的性能和功率利用率的方法。 当EASS接收到PCM信号时，以高压缩率算法对音频信号进行压缩并保存在临时存储器中，之后当从临时存储器中读出音频数据时，音频数据以相同的音频被解码 压缩算法恢复到原始的PCM格式，从而在数据读取和声音播放之间创建数据缓冲。 高压缩率算法可以增加DRAM存储器的利用率，大大延长缓冲时间。 本发明结合了EASS中具有高压缩率的音频压缩算法，以获得音频性能，功率管理和成本之间最理想的平衡点。

公开(公告)号：US20050025251A1

公开(公告)日：2005-02-03

申请号：US10660504

申请日：2003-09-12

申请人： Yuh-Chin Chang ,  Hui-Ya Chou ,  Peng-Cheng Chen ,  Hong-Tsan Lee

发明人： Yuh-Chin Chang ,  Hui-Ya Chou ,  Peng-Cheng Chen ,  Hong-Tsan Lee

IPC分类号： H03M7/38 ,  H04B14/04 ,  H04B14/06

CPC分类号： H03M7/3046 ,  H04B14/048 ,  H04B14/066

摘要： A method of optimizing the compression rate in Adaptive Differential Pulse Code Modulation (ADPCM) is disclosed. The modified pulse code modulation technique employs a prognostic code converter to generate variable length codes on top of the ADPCM coding, based on the probability of occurrence of data bits in a data sample. This variable-length coding is able to further reduce the compressed data size by increasing the compression rate of the conventional ADPCM coding.

摘要翻译： 公开了一种在自适应差分脉冲编码调制（ADPCM）中优化压缩率的方法。 基于在数据样本中发生数据位的概率，经修改的脉码调制技术采用预测码转换器在ADPCM编码之上生成可变长度码。 该可变长度编码能够通过增加常规ADPCM编码的压缩率来进一步减小压缩数据大小。

公开(公告)号：US20050081196A1

公开(公告)日：2005-04-14

申请号：US10842499

申请日：2004-05-11

申请人： Hong-Tsan Lee ,  Peng-Cheng Chen

发明人： Hong-Tsan Lee ,  Peng-Cheng Chen

IPC分类号： G06F9/44 ,  G06F9/445

CPC分类号： G06F8/66

摘要： A program redirection and modification method for embedded processors with a limited amount of SRAM sets at least one address in a program of ROM to an origin address of at least one register. To redirect the embedded processor to execute another section in the program in ROM or SRAM, a destination address of the register is set to another address of the program in ROM or a program in the SRAM. Therefore, the embedded processor sets the addresses in the register and then the program in ROM can debugged or extended to an external program.

摘要翻译： 具有有限数量的SRAM的嵌入式处理器的程序重定向和修改方法将ROM的程序中的至少一个地址设置到至少一个寄存器的原始地址。 为了重定向嵌入式处理器以在ROM或SRAM中的程序中执行另一个部分，寄存器的目的地址被设置为ROM中的程序的另一个地址或SRAM中的程序。 因此，嵌入式处理器设置寄存器中的地址，然后ROM中的程序可以调试或扩展到外部程序。

公开(公告)号：US5422806A

公开(公告)日：1995-06-06

申请号：US213924

申请日：1994-03-15

申请人： Peng-Cheng Chen ,  Terng-Huei Lai

发明人： Peng-Cheng Chen ,  Terng-Huei Lai

IPC分类号： G05B13/02 ,  G05D23/19 ,  G05B13/04

CPC分类号： G05D23/19 ,  G05B13/0265

摘要： A thermal control system for variable speed microprocessor with a piecewise estimate of temperature change. The estimate is modeled after actual temperature change measurements of a microprocessor operating at low and high speeds and is recorded in a digital format in storage registers, one set of registers for each operating frequency. A counter counts sample microprocessor clock signals for a time over which the microprocessor speed is operating at a specific speed and provides a basic count signal. This basic count signal is incremented or decremented by comparison with stored values of the piecewise estimate of temperature change. As the basic signal increases or decreases, new slopes are provided to the counter for adjusting the basic count, upwards or downwards, depending on whether the system speed is high, intermediate or low. The adjusted counter output is also fed to comparators, which monitor a desired upper and lower temperature limit. As the upper limit is approached, control logic implements a throttling algorithm to maintain temperature in the desired range. The present invention takes into account the operating history of the system in a particular environment since the system powers on, including idleness of the system.

摘要翻译： 一种用于变速微处理器的热控制系统，其具有温度变化的分段估计。 在以低速和高速运行的微处理器的实际温度变化测量之后，将估计值建模，并以数字格式记录在存储寄存器中，每组工作频率为一组寄存器。 计数器对微处理器时钟信号进行计数，一段时间内微处理器速度以特定速度运行，并提供基本计数信号。 通过与温度变化的分段估计值的存储值进行比较，该基本计数信号被递增或递减。 随着基本信号的增加或减少，根据系统速度是高，中还是低，可以向计数器提供新的斜坡，用于调整基本计数，向上或向下。 调整后的计数器输出也供给比较器，用于监控所需的上限和下限温度。 当接近上限时，控制逻辑实现节流算法，将温度保持在所需范围内。 本发明考虑到系统在系统上电后的特定环境中的操作历史，包括系统的空闲。