摘要:
A 4-to-2 carry save adder with a reduction in the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a lower order full order coupled to a higher order full adder. The carry save adder may further include a logic unit coupled to the higher order full adder where the logic unit is configured to generate a carry bit to be inputted to the higher order full adder that normally would be generated from the carry save adder located in the previous stage. By generating this carry bit (carry-in bit) in the current stage and not in the previous stage, the delay of the carry-in bit inputted to the higher order full adder is reduced thereby reducing the delay of outputting the sum and carry bits by the higher order full adder.
摘要:
A cascaded pass-gate test circuit including interposed split-output drive devices provides accurate measurement of critical timing parameters of pass gates. The rise time and fall time of signals passed through the pass gate can be separately measured in a ring oscillator or one-shot delay line configuration. Inverters or other buffer circuits are provided as drive devices to couple the pass gates in cascade. The final complementary tree in each drive device is split so that the only one of the output pull-down transistor or pull-up transistor is connected to the next pass gate input, while the other transistor is connected to the output of the pass gate. The result is that the state transition associated with the device connected to the pass gate input is dominant in the delay, while the other state transition is propagated directly to the output of the pass gate, bypassing the pass gate.
摘要:
A dynamic logic circuit incorporating reduced leakage state-retaining devices reduces power consumption of processors and other systems incorporating dynamic circuits. A keeper circuit provides a low leakage retention of the state of the output stage of the dynamic circuit so that an output circuit foot device can be disabled except when required for a transition in the output of the dynamic circuit. The keeper circuit includes a transistor having a smaller area than a corresponding transistor in the output circuit, thus reducing leakage through the gate of the output circuit when the keeper circuit is holding the output and the output circuit foot device is disabled. A self-clocked control of the output circuit foot device can be provided via a delayed version of the dynamic logic gate output, or may be provided by an external control circuit that generates a delayed version of the precharge clock or a multi-cycle signal.
摘要:
A single-stage level shifting circuit is used to interface control signals across the boundary between voltage domains with differing positive or ground voltage potentials Asserted states are determined by the difference between the positive voltages potentials and the ground potentials. A lower positive power supply potential is not used to turn OFF PFET coupled to a higher positive power supply potential. Likewise a higher ground power supply potential is not used to turn OF NFETs coupled to a power domain where is significant ground shift. The single stage level shifting circuit has keeper devices that hold asserted states using voltages within the power gated domain.
摘要:
A dynamic logic gate has an asymmetrical dual-gate PFET device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node during an evaluate phase of the clock. The front gate of the asymmetrical dual-gate PFET device is coupled to the clock signal and the back gate is coupled to the ground potential of the power supply. When the clock is a logic zero both the front gate and the back gate are biased ON and the dynamic node charges with maximum current. The clock signal transitions to a logic one during the evaluation phase of the clock turning OFF the front gate. The back gate remains ON and the asymmetrical dual-gate PFET device operates as a keeper device with a current level sufficient to counter leakage on the dynamic node.
摘要:
A dynamic logic circuit apparatus and method for reducing leakage power consumption via separate clock and output stage control reduces power consumption of processors and other systems incorporating dynamic circuits. The power control signal may be a delayed version of the logic clock and turns on the output inverter foot device after the dynamic node has had sufficient time to evaluate, providing a fast evaluate time and reducing leakage through the inverter input when the foot device is off. Alternatively, a coarsely timed static power control signal may be used to control the inverter foot devices. The drains of the inverter foot devices can be commonly connected across multiple circuits, reducing the foot device total area.
摘要:
Methods and arrangements to configure power management systems for integrated circuits are provided herein. A group of IC components that are functionally distinct or have mutually exclusive and/or quasi-mutually exclusive, (ME/QME) operating patterns (i.e. alternate or partially overlapping duty cycles) can be powered with a single power cell. An integrated circuit design tool can identified components in an integrated circuit design that have the ME/QME operating patterns. These cells can be collocated in close proximity to each other and power management system components can be placed in this area such that a multiple signal processing cells can share a single power line and a single power cell. Such a configuration can greatly reduce the size of a power management system for an integrated circuit.
摘要:
Virtual power-gated cells (VPC) are configured with control circuitry for buffering control signals and a power-gated block (PGB) comprising two or more NFETs for virtual ground rail nodes and PFETs for virtual positive rail nodes. Each VPC has a control voltage input, a control voltage output, a node coupled to a power supply voltage potential, and a virtual power-gated node that is coupled and decoupled from the power supply potential in response to logic states on the control input. The control signals are buffered by non-power-gated inverters before being applied to the input of a PGB. VPCs may propagate a control signal that is in phase with or inverted from a corresponding control signal at the control input. VPCs may be cascaded to create virtual power rails in chains and power grids. The control signals are latched at the cell boundaries or latched in response to a clock signal.
摘要:
An LSDL circuit is improved by having the data input function to control the pre-charging of the dynamic node. The clock signal no longer is coupled to the P channel FET used to pre-charge the dynamic node. Additionally an N channel FET (NFET) is added in parallel with the NFET coupled to the clock for evaluating the dynamic node. This NFET assures the dynamic node does not float when the data input is a logic one and the clock is a logic zero.
摘要:
A cascaded test circuit with inter-bitline drive devices for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A row in a memory array is enabled along with a set of drive devices that couple each bitline pair to the next in complement fashion to form a cascade of memory cells. The drive devices can be inverters and the inverters can be sized to simulate the bitline read pre-charge device and the write state-forcing device so that the cascade operates under the same loading/drive conditions as the operational with memory cell read/write circuits. The last and first bitline in the row can be cascaded, providing a ring oscillator or the delay of the cascade can be measured in response to a transition introduced at the head of the cascade. Weak read and/or weak write conditions can be measured by selective loading.