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公开(公告)号：US08271912B2
公开(公告)日：2012-09-18
申请号：US12051002
申请日：2008-03-19
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/62
摘要： A method for designing integrated circuits uses clock signal interleaving to reduce the likelihood of a soft error arising from an upset in a clock distribution network. At least two circuits in a circuit description are identified as being sensitive to radiation, and different clock distribution nodes are assigned to the two circuits. Several exemplary implementations are disclosed. The second circuit may be a redundant replica of the first circuit, such as a reset circuit. The first and second circuits may be components of a modular redundant circuit such as a triple modular redundancy flip-flop. The first circuit may include a set of data bits for an entry of a storage array such as a register or memory array, and the second circuit may include a set of check bits associated with the entry.
摘要翻译： 一种设计集成电路的方法使用时钟信号交织来减少由时钟分配网络中的不适引起的软错误的可能性。 电路描述中的至少两个电路被识别为对辐射敏感，并且不同的时钟分配节点被分配给两个电路。 公开了几个示例性实现。 第二电路可以是第一电路的冗余复制品，例如复位电路。 第一和第二电路可以是模块化冗余电路的组件，例如三模块冗余触发器。 第一电路可以包括用于诸如寄存器或存储器阵列的存储阵列的入口的一组数据位，并且第二电路可以包括与该条目相关联的一组校验位。
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2.发明授权Method for QCRIT measurement in bulk CMOS using a switched capacitor circuit 有权使用开关电容电路的批量CMOS QCRIT测量方法公开(公告)号：US07881135B2
公开(公告)日：2011-02-01
申请号：US11679406
申请日：2007-02-27
IPC分类号： G11C29/00
CPC分类号： G01R31/318594 , G01R31/318597
摘要： A test setup for estimating the critical charge of a circuit under test (CUT) uses a charge injection circuit having a switched capacitor that is selectively connected to a node of the CUT. A voltage measurement circuit measures the voltage at a tap in the charge injection circuit before and after the charge is injected. When the injected charge causes an upset in the logical state of the CUT, the critical charge is calculated as the product of the voltage difference and the known capacitance of the capacitor. In one embodiment, (NMOS drain strike simulation) the amount of charge injected is controlled by a variable pulse width generator gating the switch of the charge injection circuit. In another embodiment (PMOS drain strike simulation) the amount of charge injected is controlled by a variable voltage supply selectively connected to the charge storage node.
摘要翻译： 用于估计被测电路的临界电荷的测试装置（CUT）使用具有选择性地连接到CUT的节点的开关电容器的电荷注入电路。 电压测量电路测量电荷注入前后电荷注入电路中的电压。 当注入的电荷导致CUT的逻辑状态不正常时，临界电荷被计算为电压差和电容器的已知电容的乘积。 在一个实施例中，（NMOS漏极击穿模拟）通过门控电荷注入电路的开关的可变脉冲宽度发生器来控制注入的电荷量。 在另一实施例（PMOS漏极击穿模拟）中，注入的电荷量由选择性地连接到电荷存储节点的可变电压电源来控制。
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公开(公告)号：US20090241073A1
公开(公告)日：2009-09-24
申请号：US12051002
申请日：2008-03-19
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/62
摘要： A method for designing integrated circuits uses clock signal interleaving to reduce the likelihood of a soft error arising from an upset in a clock distribution network. At least two circuits in a circuit description are identified as being sensitive to radiation, and different clock distribution nodes are assigned to the two circuits. Several exemplary implementations are disclosed. The second circuit may be a redundant replica of the first circuit, such as a reset circuit. The first and second circuits may be components of a modular redundant circuit such as a triple modular redundancy flip-flop. The first circuit may include a set of data bits for an entry of a storage array such as a register or memory array, and the second circuit may include a set of check bits associated with the entry.
摘要翻译： 一种设计集成电路的方法使用时钟信号交织来减少由时钟分配网络中的不适引起的软错误的可能性。 电路描述中的至少两个电路被识别为对辐射敏感，并且不同的时钟分配节点被分配给两个电路。 公开了几个示例性实现。 第二电路可以是第一电路的冗余复制品，例如复位电路。 第一和第二电路可以是模块化冗余电路的组件，例如三模块冗余触发器。 第一电路可以包括用于诸如寄存器或存储器阵列的存储阵列的入口的一组数据位，并且第二电路可以包括与该条目相关联的一组校验位。
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公开(公告)号：US20090179193A1
公开(公告)日：2009-07-16
申请号：US11972669
申请日：2008-01-11
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L51/0541 , B82Y10/00 , H01L27/11 , H01L27/1104 , H01L27/283 , H01L51/0048 , H01L51/0558 , Y10S977/742 , Y10S977/75 , Y10S977/751 , Y10S977/752
摘要： Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the carbon nanotube, forming a reverse biased junction of a hole-induced region and an electron-induced region of the carbon nanotube, or electrically biasing a region through a dielectric layer between two device regions of the carbon nanotube. The carbon nanotubes may be arranged such that hole-inducing material layer and electron-inducing material layer may be assigned to each carbon nanotube to form periodic structures such as a static random access memory (SRAM) array.
摘要翻译： 在半导体碳纳米管上形成栅电极，然后根据一维电路布局的图案在碳纳米管上沉积和图案化空穴诱导材料层和电子诱导材料层。 可以通过切割碳纳米管的一部分来形成电气隔离，形成空穴诱导区域和碳纳米管的电子诱导区域的反向偏置接合点，或者通过介电层在两个器件区域之间电气偏置区域 碳纳米管。 碳纳米管可以被布置为使得可以将空穴诱导材料层和电子诱导材料层分配给每个碳纳米管以形成诸如静态随机存取存储器（SRAM）阵列的周期性结构。
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5.发明授权公开(公告)号：US07193446B2
公开(公告)日：2007-03-20
申请号：US10992486
申请日：2004-11-18
IPC分类号： H03K19/094
CPC分类号： H03K19/0963 , H03K19/0016
摘要： A dynamic logic circuit incorporating reduced leakage state-retaining devices reduces power consumption of processors and other systems incorporating dynamic circuits. A keeper circuit provides a low leakage retention of the state of the output stage of the dynamic circuit so that an output circuit foot device can be disabled except when required for a transition in the output of the dynamic circuit. The keeper circuit includes a transistor having a smaller area than a corresponding transistor in the output circuit, thus reducing leakage through the gate of the output circuit when the keeper circuit is holding the output and the output circuit foot device is disabled. A self-clocked control of the output circuit foot device can be provided via a delayed version of the dynamic logic gate output, or may be provided by an external control circuit that generates a delayed version of the precharge clock or a multi-cycle signal.
摘要翻译： 结合减少泄漏状态保持装置的动态逻辑电路降低了处理器和其他结合动态电路的系统的功耗。 保持器电路提供动态电路的输出级的状态的低泄漏保持，使得输出电路脚装置可以被禁用，除非在动态电路的输出中需要转换。 保持器电路包括具有比输出电路中的对应晶体管更小的面积的晶体管，从而当保持器电路保持输出并且输出电路脚器件被禁用时减小通过输出电路的栅极的泄漏。 可以通过延迟版本的动态逻辑门输出来提供输出电路脚装置的自定时控制，或者可以由产生预充电时钟的延迟版本或多周期信号的外部控制电路提供。
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公开(公告)号：US08354858B2
公开(公告)日：2013-01-15
申请号：US12987106
申请日：2011-01-08
申请人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
发明人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
IPC分类号： G01R31/26
CPC分类号： H03K3/356156 , H03K3/0375
摘要： A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.
摘要翻译： 确定特定电路内分别被硬化晶体管替代的一个或多个晶体管的方法包括：鉴定为不需要硬化一个或多个晶体管; 识别作为硬化的候选者，电路中的每个晶体管先前未被识别为不需要硬化; 并且使用硬化晶体管代替被鉴定为硬化候选的晶体管。 该电路是锁存器，晶体管是SOI CMOS FET。 晶体管也是SOI晶体管。 串联晶体管包括具有共享源极/漏极区域的第一和第二串联连接的晶体管，由此第一串联晶体管的漏极与第二串联晶体管的源极合并。
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公开(公告)号：US07888959B2
公开(公告)日：2011-02-15
申请号：US11857596
申请日：2007-09-19
申请人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
发明人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
IPC分类号： G01R31/26
CPC分类号： H03K3/356156 , H03K3/0375
摘要： A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.
摘要翻译： 确定特定电路内分别被硬化晶体管替代的一个或多个晶体管的方法包括：鉴定为不需要硬化一个或多个晶体管; 识别作为硬化的候选者，电路中的每个晶体管先前未被识别为不需要硬化; 并且使用硬化晶体管代替被鉴定为硬化候选的晶体管。 该电路是锁存器，晶体管是SOI CMOS FET。 晶体管也是SOI晶体管。 串联晶体管包括具有共享源极/漏极区域的第一和第二串联连接的晶体管，由此第一串联晶体管的漏极与第二串联晶体管的源极合并。
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8.发明申请Method for Qcrit Measurement in Bulk CMOS Using a Switched Capacitor Circuit 有权使用开关电容电路的批量CMOS中的Qcrit测量方法公开(公告)号：US20100271057A1
公开(公告)日：2010-10-28
申请号：US11679406
申请日：2007-02-27
IPC分类号： G01R31/30
CPC分类号： G01R31/318594 , G01R31/318597
摘要： A test setup for estimating the critical charge of a circuit under test (CUT) uses a charge injection circuit having a switched capacitor that is selectively connected to a node of the CUT. A voltage measurement circuit measures the voltage at a tap in the charge injection circuit before and after the charge is injected. When the injected charge causes an upset in the logical state of the CUT, the critical charge is calculated as the product of the voltage difference and the known capacitance of the capacitor. In one embodiment, (NMOS drain strike simulation) the amount of charge injected is controlled by a variable pulse width generator gating the switch of the charge injection circuit. In another embodiment (PMOS drain strike simulation) the amount of charge injected is controlled by a variable voltage supply selectively connected to the charge storage node.
摘要翻译： 用于估计被测电路的临界电荷的测试装置（CUT）使用具有选择性地连接到CUT的节点的开关电容器的电荷注入电路。 电压测量电路测量电荷注入前后电荷注入电路中的电压。 当注入的电荷导致CUT的逻辑状态不正常时，临界电荷被计算为电压差和电容器的已知电容的乘积。 在一个实施例中，（NMOS漏极击穿模拟）通过门控电荷注入电路的开关的可变脉冲宽度发生器来控制注入的电荷量。 在另一实施例（PMOS漏极击穿模拟）中，注入的电荷量由选择性地连接到电荷存储节点的可变电压电源来控制。
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公开(公告)号：US07786466B2
公开(公告)日：2010-08-31
申请号：US11972669
申请日：2008-01-11
IPC分类号： H01L51/00
CPC分类号： H01L51/0541 , B82Y10/00 , H01L27/11 , H01L27/1104 , H01L27/283 , H01L51/0048 , H01L51/0558 , Y10S977/742 , Y10S977/75 , Y10S977/751 , Y10S977/752
摘要： Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the carbon nanotube, forming a reverse biased junction of a hole-induced region and an electron-induced region of the carbon nanotube, or electrically biasing a region through a dielectric layer between two device regions of the carbon nanotube. The carbon nanotubes may be arranged such that hole-inducing material layer and electron-inducing material layer may be assigned to each carbon nanotube to form periodic structures such as a static random access memory (SRAM) array.
摘要翻译： 在半导体碳纳米管上形成栅电极，然后根据一维电路布局的图案在碳纳米管上沉积和图案化空穴诱导材料层和电子诱导材料层。 可以通过切割碳纳米管的一部分来形成电气隔离，形成空穴诱导区域和碳纳米管的电子诱导区域的反向偏置接合点，或者通过介电层在两个器件区域之间电气偏置区域 碳纳米管。 碳纳米管可以被布置为使得可以将空穴诱导材料层和电子诱导材料层分配给每个碳纳米管以形成诸如静态随机存取存储器（SRAM）阵列的周期性结构。
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公开(公告)号：US07774732B2
公开(公告)日：2010-08-10
申请号：US11838368
申请日：2007-08-14
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of designing a layout of an integrated circuit for increased radiation tolerance by ensuring that any critical components (those deemed particularly sensitive to radiation-induced soft errors) are at spacings greater than a predetermined threshold based on particle migration within the silicon substrate. The method starts with an initial placement, identifies the objects for which radiation tolerance is desired, determines whether any of those objects and, if so, moves the relevant objects to increase the spacing. An exemplary threshold for contemporary CMOS device technologies is 5 μm. The objects can be moved by vertically and/or horizontally shifting away from a reference point of the integrated circuit. The critical objects may include triplicated (redundant) structures, clock control latches, or a reset bit. The method can be used in conjunction with other placement optimizations such as area, power and timing.
摘要翻译： 通过确保任何关键部件（被认为对辐射引起的软错误特别敏感的部件）基于硅衬底内的粒子迁移而大于预定阈值的间隔，设计集成电路的布局以提高辐射耐受性的方法。 该方法从初始放置开始，识别期望辐射公差的对象，确定是否有任何这些对象，如果是，移动相关对象以增加间距。 现代CMOS器件技术的典型阈值为5μm。 物体可以通过垂直和/或水平移动远离集成电路的参考点移动。 关键对象可以包括三重（冗余）结构，时钟控制锁存器或复位位。 该方法可以与其他布局优化（如面积，功率和时序）结合使用。
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