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公开(公告)号：US06897712B2
公开(公告)日：2005-05-24
申请号：US10604799
申请日：2003-08-18
CPC分类号： H03K5/19 , H03K5/08 , H04L25/0272 , H04L25/085
摘要： An apparatus and method is provided for detecting loss of differential signal carried by a pair of differential signal lines. According to the method, a common mode level is detected from voltages on the pair of differential signal lines. A threshold level is generated, referenced to the detected common mode level. A signal level is generated from the voltages on the pair of differential signal lines, the signal level being averaged over a first period of time. From the threshold level and the detected common mode level a reference level is generated, the reference level being averaged over a second period of time longer than then the first period of time. The signal level is compared to the reference level to determine if a signal is present on the pair of differential signal lines.
摘要翻译： 提供一种用于检测由一对差分信号线携带的差分信号的损耗的装置和方法。 根据该方法，从该对差分信号线上的电压检测共模电平。 产生阈值电平，参考检测到的共模电平。 信号电平由一对差分信号线上的电压产生，信号电平在第一时间段内被平均化。 从阈值电平和检测到的共模电平产生参考电平，在比第一时间段长的第二时间段内平均参考电平。 将信号电平与参考电平进行比较，以确定信号对是否存在于该对差分信号线上。
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公开(公告)号：US08027416B2
公开(公告)日：2011-09-27
申请号：US12043166
申请日：2008-03-06
IPC分类号： H04L27/08
CPC分类号： H04L25/063 , H04L25/0292
摘要： A machine-readable medium thereupon stored a design structure; the design structure includes a receiver for a data communications system. The receiver includes a data path for receiving a data signal from a data channel, the data path comprising an automatic gain control (AGC) loop; and, a signal detector for generating a data valid signal indicative of the validity of the data signal in response to detection of the data signal on the channel exceeding a threshold and in dependence upon gain information from the AGC loop in the data path.
摘要翻译： 机器可读介质存储设计结构; 该设计结构包括用于数据通信系统的接收器。 接收机包括用于从数据信道接收数据信号的数据路径，数据路径包括自动增益控制（AGC）环路; 以及信号检测器，用于响应于在信道上的数据信号的检测超过阈值并且根据来自数据路径中的AGC循环的增益信息，产生指示数据信号的有效性的数据有效信号。
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公开(公告)号：US20080037690A1
公开(公告)日：2008-02-14
申请号：US11737319
申请日：2007-04-19
CPC分类号： H04L25/0292 , H04L25/063
摘要： A receiver for a data communications system comprises: a data path for receiving a data signal from a data channel, the data path comprising an automatic gain control (AGC) loop; and, a signal detector for generating a data valid signal indicative of the validity of the data signal in response to detection of the data signal on the channel exceeding a threshold and in dependence upon gain information from the AGC loop in the data path.
摘要翻译： 用于数据通信系统的接收机包括：用于从数据信道接收数据信号的数据路径，所述数据路径包括自动增益控制（AGC）环路; 以及信号检测器，用于响应于在信道上的数据信号的检测超过阈值并且根据来自数据路径中的AGC循环的增益信息，产生指示数据信号的有效性的数据有效信号。
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公开(公告)号：US08027415B2
公开(公告)日：2011-09-27
申请号：US11737319
申请日：2007-04-19
IPC分类号： H04L27/08
CPC分类号： H04L25/0292 , H04L25/063
摘要： A receiver for a data communications system comprises: a data path for receiving a data signal from a data channel, the data path comprising an automatic gain control (AGC) loop; and, a signal detector for generating a data valid signal indicative of the validity of the data signal in response to detection of the data signal on the channel exceeding a threshold and in dependence upon gain information from the AGC loop in the data path.
摘要翻译： 用于数据通信系统的接收机包括：用于从数据信道接收数据信号的数据路径，所述数据路径包括自动增益控制（AGC）环路; 以及信号检测器，用于响应于在信道上的数据信号的检测超过阈值并且根据来自数据路径中的AGC循环的增益信息，产生指示数据信号的有效性的数据有效信号。
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公开(公告)号：US07840916B2
公开(公告)日：2010-11-23
申请号：US11985966
申请日：2007-11-19
申请人： Louis L. Hsu , Hayden C. Cranford, Jr. , Oleg Gluschenkov , James S. Mason , Michael A. Sorna , Chih-Chao Yang
发明人： Louis L. Hsu , Hayden C. Cranford, Jr. , Oleg Gluschenkov , James S. Mason , Michael A. Sorna , Chih-Chao Yang
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G01R31/2858
摘要： A design structure embodied in a machine readable medium used in a design process can include apparatus of a semiconductor chip operable to detect an increase in resistance of a monitored element of the semiconductor chip. The design structure can include, for example, a resistive voltage divider circuit operable to output a plurality of reference voltages having different values. A plurality of comparators in the semiconductor chip may be coupled to receive the reference voltages and a monitored voltage representative of a resistance of the monitored element. Each of the comparators may produce an output indicating whether the monitored voltage exceeds the reference voltages, so that the resistance value of the monitored element may be precisely determined.
摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构可以包括半导体芯片的装置，其可操作以检测半导体芯片的被监测元件的电阻的增加。 该设计结构可以包括例如可操作以输出具有不同值的多个参考电压的电阻分压器电路。 可以将半导体芯片中的多个比较器耦合以接收参考电压和表示所监视元件的电阻的监视电压。 每个比较器可以产生指示监视的电压是否超过参考电压的输出，使得可以精确地确定被监视元件的电阻值。
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公开(公告)号：US08089285B2
公开(公告)日：2012-01-03
申请号：US12396512
申请日：2009-03-03
CPC分类号： H01L23/576 , H01L2224/48091 , H01L2924/1461 , H01L2924/00014 , H01L2924/00
摘要： A method and tamper resistant circuit for resisting tampering including reverse engineering in a semiconductor chip, and a design structure on which the subject circuit resides are provided. A sensing device for detecting a chip tampering state is formed with the semiconductor chip including the circuitry to be protected. A tamper resistant control signal generator is coupled to the sensing unit for generating a tamper resistant control signal responsive to a detected chip tampering state. A functional operation inhibit circuit is coupled to the tamper resistant control signal generator for inhibiting functional operation of the circuitry to be protected responsive to the tamper resistant control signal.
摘要翻译： 提供一种用于抵抗篡改的方法和防篡改电路，包括半导体芯片中的逆向工程，以及设置有被摄体电路的设计结构。 用于检测芯片篡改状态的感测装置由包括待保护电路的半导体芯片形成。 防篡改控制信号发生器耦合到感测单元，用于响应于检测到的芯片篡改状态产生防篡改控制信号。 功能操作禁止电路耦合到防篡改控制信号发生器，用于响应于防篡改控制信号而禁止要被保护的电路的功能操作。
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公开(公告)号：US07719302B2
公开(公告)日：2010-05-18
申请号：US12215732
申请日：2008-06-30
申请人： Louis L. Hsu , Hayden C. Cranford, Jr. , Oleg Gluschenkov , James S. Mason , Michael A. Sorna , Chih-Chao Yang
发明人： Louis L. Hsu , Hayden C. Cranford, Jr. , Oleg Gluschenkov , James S. Mason , Michael A. Sorna , Chih-Chao Yang
IPC分类号： G01R31/02
CPC分类号： G01R31/2858 , G01R31/2884 , G01R31/318533
摘要： A method is provided for monitoring interconnect resistance within a semiconductor chip assembly, A semiconductor chip assembly can include a semiconductor chip having contacts exposed at a surface of the semiconductor chip and a substrate having exposed terminals in conductive communication with the contacts. A plurality of monitored elements of the semiconductor chip can include conductive interconnects, each interconnecting a respective pair of nodes of the semiconductor chip through wiring within the semiconductor chip. In an example of such method, a voltage drop across each monitored element is compared with a reference voltage drop across a respective reference element on the semiconductor chip at a plurality of different times during a lifetime of the semiconductor chip assembly. In that way, it can be detected when a resistance of such monitored element is over threshold. Based on a result of such comparison, a decision can be made whether to indicate an action condition.
摘要翻译： 提供了一种用于监测半导体芯片组件内的互连电阻的方法。半导体芯片组件可以包括具有在半导体芯片的表面处露出的触点的半导体芯片和具有与触点导电连通的露出端子的基板。 半导体芯片的多个受监测元件可以包括导电互连，每个导体互连通过半导体芯片内的布线互连半导体芯片的相应的一对节点。 在这种方法的示例中，在半导体芯片组件的寿命期间，跨越每个被监测元件的电压降与在半导体芯片上的相应参考元件上的参考电压降在多个不同时间进行比较。 以这种方式，当这种被监视的元件的电阻超过阈值时，可以检测它。 基于这种比较的结果，可以做出是否指示动作条件的决定。
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公开(公告)号：US07519130B2
公开(公告)日：2009-04-14
申请号：US10905705
申请日：2005-01-18
申请人： Louis L. Hsu , Matt R. Cordrey-Gale , James S. Mason , Philip J. Murfet , Karl D. Selander , Michael A. Sorna , Huihao Xu
发明人： Louis L. Hsu , Matt R. Cordrey-Gale , James S. Mason , Philip J. Murfet , Karl D. Selander , Michael A. Sorna , Huihao Xu
IPC分类号： H04L25/34
CPC分类号： H04L25/0274 , H04L25/0296
摘要： A data receiver is provided which includes a front end interface circuit having an alternating current (AC) transmission receiving mode and a direct current (DC) transmission receiving mode. The front end interface circuit includes an offset compensation circuit operable to compensate a DC voltage offset between a pair of differential signals input to the data receiver. The front end interface circuit further includes an AC/DC selection unit operable to switch between (a) the DC transmission receiving mode, and (b) the AC transmission receiving mode, such that the data receiver is operable in (i) the DC transmission mode in which the offset compensation circuit is disabled, (ii) the DC transmission mode in which the offset compensation circuit is enabled, (iii) the AC transmission mode in which the offset compensation circuit is disabled, and (iv) the AC transmission receiving mode in which the offset compensation circuit is enabled.
摘要翻译： 提供一种数据接收器，其包括具有交流（AC）发送接收模式和直流（DC）发送接收模式的前端接口电路。 前端接口电路包括偏移补偿电路，其可操作以补偿输入到数据接收器的一对差分信号之间的直流电压偏移。 前端接口电路还包括可操作以在（a）直流发送接收模式和（b）交流发送接收模式之间切换的AC / DC选择单元，使得数据接收器可操作于（i）直流传输 偏移补偿电路被禁用的模式，（ii）使能偏移补偿电路的直流传输模式，（iii）偏移补偿电路被禁用的AC传输模式，以及（iv）AC传输接收 偏移补偿电路使能的模式。
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公开(公告)号：US20100225380A1
公开(公告)日：2010-09-09
申请号：US12396512
申请日：2009-03-03
IPC分类号： H03K17/78
CPC分类号： H01L23/576 , H01L2224/48091 , H01L2924/1461 , H01L2924/00014 , H01L2924/00
摘要： A method and tamper resistant circuit for resisting tampering including reverse engineering in a semiconductor chip, and a design structure on which the subject circuit resides are provided. A sensing device for detecting a chip tampering state is formed with the semiconductor chip including the circuitry to be protected. A tamper resistant control signal generator is coupled to the sensing unit for generating a tamper resistant control signal responsive to a detected chip tampering state. A functional operation inhibit circuit is coupled to the tamper resistant control signal generator for inhibiting functional operation of the circuitry to be protected responsive to the tamper resistant control signal.
摘要翻译： 提供一种用于抵抗篡改的方法和防篡改电路，包括半导体芯片中的逆向工程，以及设置有被摄体电路的设计结构。 用于检测芯片篡改状态的感测装置由包括待保护电路的半导体芯片形成。 防篡改控制信号发生器耦合到感测单元，用于响应于检测到的芯片篡改状态产生防篡改控制信号。 功能操作禁止电路耦合到防篡改控制信号发生器，用于响应于防篡改控制信号而禁止要被保护的电路的功能操作。
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公开(公告)号：US20090132985A1
公开(公告)日：2009-05-21
申请号：US11985966
申请日：2007-11-19
申请人： Louis L. Hsu , Hayden C. Cranford, JR. , Oleg Gluschenkov , James S. Mason , Michael A. Sorna , Chih-Chao Yang
发明人： Louis L. Hsu , Hayden C. Cranford, JR. , Oleg Gluschenkov , James S. Mason , Michael A. Sorna , Chih-Chao Yang
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G01R31/2858
摘要： A design structure embodied in a machine readable medium used in a design process can include apparatus of a semiconductor chip operable to detect an increase in resistance of a monitored element of the semiconductor chip. The design structure can include, for example, a resistive voltage divider circuit operable to output a plurality of reference voltages having different values. A plurality of comparators in the semiconductor chip may be coupled to receive the reference voltages and a monitored voltage representative of a resistance of the monitored element. Each of the comparators may produce an output indicating whether the monitored voltage exceeds the reference voltages, so that the resistance value of the monitored element may be precisely determined.
摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构可以包括半导体芯片的装置，其可操作以检测半导体芯片的被监测元件的电阻的增加。 该设计结构可以包括例如可操作以输出具有不同值的多个参考电压的电阻分压器电路。 可以将半导体芯片中的多个比较器耦合以接收参考电压和表示所监视元件的电阻的监视电压。 每个比较器可以产生指示监视的电压是否超过参考电压的输出，使得可以精确地确定被监视元件的电阻值。
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