Rebuild Assist Using Failed Storage Device
    1.
    发明申请

    公开(公告)号:US20200042389A1

    公开(公告)日:2020-02-06

    申请号:US16054972

    申请日:2018-08-03

    摘要: Methods, systems, and other aspects for reconstructing data and rebuilding a failed storage device in a storage system using one or more functioning compute resources and/or storage resources of the failed storage device. For example, a method may include, responsive to a detection of a failed storage device in a storage system, locating data and redundancy information in functioning storage device(s) in the storage system for reconstructing data of the failed storage device; issuing peer-to-peer commands to the functioning storage device(s) to obtain the data and the redundancy information from the functioning storage device(s); and reconstructing the data of the failed storage device based on the data and the redundancy information obtained from the functioning storage device(s), wherein a functioning compute resource of the failed computing device at least partially performs one or more of the locating, issuing, and reconstructing.

    Offloaded Disaggregated Storage Architecture

    公开(公告)号:US20180341606A1

    公开(公告)日:2018-11-29

    申请号:US15936319

    申请日:2018-03-26

    IPC分类号: G06F13/28 G06F3/06 G06F13/16

    摘要: Data management functions are offloaded from a main controller to individual storage devices in a multi-device storage environment. The main controller receives a data management request from a host system, and responds by determining one or more storage devices and one or more data management operations to be performed by the one or more storage devices. The main controller initiates performance of a data management function corresponding to the data management request, by sending one or more data management commands to the one or more storage devices, and initiating one or more data transfers, such as a direct memory access operation to transfer data between a memory buffer of a storage device and a host memory buffer of the host system, and an internal data transfer between two or more of the storage devices using an internal communication fabric of the data storage sub system.

    Accelerating binary neural networks within latch structure of non-volatile memory devices

    公开(公告)号:US11544547B2

    公开(公告)日:2023-01-03

    申请号:US16908576

    申请日:2020-06-22

    摘要: A non-volatile memory device includes an array of non-volatile memory cells that are configured to store weights of a neural network. Associated with the array is a data latch structure that includes a page buffer, which can store weights for a layer of the neural network that is read out of the array, and a transfer buffer, that can store inputs for the neural network. The memory device can perform multiply and accumulate operations between inputs and weight of the neural network within the latch structure, avoiding the need to transfer data out of the array and associated latch structure for portions of an inference operation. By using binary weights and inputs, multiplication can be performed by bit-wise XNOR operations. The results can then be summed and activation applied, all within the latch structure.

    ACCELERATING BINARY NEURAL NETWORKS WITHIN LATCH STRUCTURE OF NON-VOLATILE MEMORY DEVICES

    公开(公告)号:US20210397930A1

    公开(公告)日:2021-12-23

    申请号:US16908576

    申请日:2020-06-22

    摘要: A non-volatile memory device includes an array of non-volatile memory cells that are configured to store weights of a neural network. Associated with the array is a data latch structure that includes a page buffer, which can store weights for a layer of the neural network that is read out of the array, and a transfer buffer, that can store inputs for the neural network. The memory device can perform multiply and accumulate operations between inputs and weight of the neural network within the latch structure, avoiding the need to transfer data out of the array and associated latch structure for portions of an inference operation. By using binary weights and inputs, multiplication can be performed by bit-wise XNOR operations. The results can then be summed and activation applied, all within the latch structure.

    MEMORY PREFETCH BASED ON MACHINE LEARNING
    6.
    发明公开

    公开(公告)号:US20240193088A1

    公开(公告)日:2024-06-13

    申请号:US18231730

    申请日:2023-08-08

    IPC分类号: G06F12/0862 G06N20/00

    CPC分类号: G06F12/0862 G06N20/00

    摘要: A memory device includes a first memory and a second memory that caches data stored in the first memory. At least one controller of the memory device receives page fault information from a host. The page fault information results from a request for data by the host that is stored in the first memory but is not cached in the second memory when requested by the host. The memory device uses the received page fault information for one or more inputs into a prefetch model trained by Machine Learning (ML) to generate at least one inference. Based at least in part on the at least one inference, prefetch data is cached in the second memory. In one aspect, the page fault information is used to train the prefetch model. In another aspect, the page fault information includes at least one virtual address used by the host for the requested data.

    Rebuild assist using failed storage device

    公开(公告)号:US10831603B2

    公开(公告)日:2020-11-10

    申请号:US16054972

    申请日:2018-08-03

    摘要: Methods, systems, and other aspects for reconstructing data and rebuilding a failed storage device in a storage system using one or more functioning compute resources and/or storage resources of the failed storage device. For example, a method may include, responsive to a detection of a failed storage device in a storage system, locating data and redundancy information in functioning storage device(s) in the storage system for reconstructing data of the failed storage device; issuing peer-to-peer commands to the functioning storage device(s) to obtain the data and the redundancy information from the functioning storage device(s); and reconstructing the data of the failed storage device based on the data and the redundancy information obtained from the functioning storage device(s), wherein a functioning compute resource of the failed computing device at least partially performs one or more of the locating, issuing, and reconstructing.

    Flexible accelerator for sparse tensors in convolutional neural networks

    公开(公告)号:US11462003B2

    公开(公告)日:2022-10-04

    申请号:US16830167

    申请日:2020-03-25

    摘要: A system with a multiplication circuit having a plurality of multipliers is disclosed. Each of the plurality of multipliers is configured to receive a data value and a weight value to generate a product value in a convolution operation of a machine learning application. The system also includes an accumulator configured to receive the product value from each of the plurality of multipliers and a register bank configured to store an output of the convolution operation. The accumulator is further configured to receive a portion of values stored in the register bank and combine the received portion of values with the product values to generate combined values. The register bank is further configured to replace the portion of values with the combined values.

    FLEXIBLE ACCELERATOR FOR SPARSE TENSORS IN CONVOLUTIONAL NEURAL NETWORKS

    公开(公告)号:US20210303976A1

    公开(公告)日:2021-09-30

    申请号:US16830129

    申请日:2020-03-25

    IPC分类号: G06N3/063 G06N3/04 G06N3/08

    摘要: An apparatus includes a tensor compute cluster having a plurality of tensor compute units to process a plurality of sub-feature maps in a machine learning application and a tensor memory cluster having a plurality of tensor feature map memory units to store the plurality of sub-feature maps. The apparatus also includes circuitry to partition an input feature map into the plurality of sub-feature maps such that sparsity in each of the plurality of sub-feature maps satisfies a predetermined threshold, and assign each of the plurality of sub-feature maps to one of the plurality of tensor compute units and one of the plurality of tensor feature map memory units for processing in parallel.