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    Interface bus speed optimization
    1.
    发明授权
    Interface bus speed optimization 有权

    公开(公告)号：US11984192B2

    公开(公告)日：2024-05-14

    申请号：US17841432

    申请日：2022-06-15

    Applicant: Western Digital Technologies, Inc.

    Inventor： Mordekhay Zehavi ,  Mahmud Asfur ,  Yossef Tamir ,  Yuri Ryabinin

    IPC: G11C7/10 ,  G11C5/14 ,  G11C7/22 ,  G11C29/52

    CPC classification number: G11C7/1048 ,  G11C5/14 ,  G11C7/1039 ,  G11C7/22 ,  G11C29/52

    Abstract: Various devices, such as storage devices or systems are configured to transmit data between various components over one or more interfaces. The operation of these interfaces is based on the mechanical limits of the components doing the communication, often latches. Latches often require a setup and hold time limit on the signal being transmitted to be held a desired value. Because the physical effects of the environment, such as voltage being provided, temperature of the component, for example, can affect the operation of the latch, there is often a large margin used to operate them. These large margins avoid errors but decrease overall speed of the interface. By utilizing a test latch within an interface bus group with a drop in operating voltage, changes in output detected can be indicative of upcoming errors. Once detected, the error can be remedied by increasing voltage, lowering operating speeds, or cooling the components.

    Interface Bus Speed Optimization
    2.
    发明公开
    Interface Bus Speed Optimization 审中-公开

    公开(公告)号：US20230410858A1

    公开(公告)日：2023-12-21

    申请号：US17841432

    申请日：2022-06-15

    Applicant: Western Digital Technologies, Inc.

    Inventor： Mordekhay Zehavi ,  Mahmud Asfur ,  Yossef Tamir ,  Yuri Ryabinin

    IPC: G11C7/10 ,  G11C7/22 ,  G11C5/14 ,  G11C29/52

    CPC classification number: G11C7/1048 ,  G11C7/1039 ,  G11C7/22 ,  G11C5/14 ,  G11C29/52

    Abstract: Various devices, such as storage devices or systems are configured to transmit data between various components over one or more interfaces. The operation of these interfaces is based on the mechanical limits of the components doing the communication, often latches. Latches often require a setup and hold time limit on the signal being transmitted to be held a desired value. Because the physical effects of the environment, such as voltage being provided, temperature of the component, for example, can affect the operation of the latch, there is often a large margin used to operate them. These large margins avoid errors but decrease overall speed of the interface. By utilizing a test latch within an interface bus group with a drop in operating voltage, changes in output detected can be indicative of upcoming errors. Once detected, the error can be remedied by increasing voltage, lowering operating speeds, or cooling the components.

    High throughput, low power, high parity architecture for database SSD
    3.
    发明授权
    High throughput, low power, high parity architecture for database SSD 有权

    公开(公告)号：US11537534B2

    公开(公告)日：2022-12-27

    申请号：US17181907

    申请日：2021-02-22

    Applicant: Western Digital Technologies, Inc.

    Inventor： Israel Zimmerman ,  Mahmud Asfur ,  Mordekhay Zehavi

    IPC: G06F13/16 ,  G06F15/80 ,  H03M13/11 ,  G06F16/23 ,  G06F11/10

    Abstract: A method and apparatus for the increase of internal data throughput and processing capability for SSD's, to enable processing of database commands on an SSD. A front-end ASIC is provided with 256 to 512 RISC processing cores to enable decomposition and parallelization of host commands to front-end module (FM) ASICs that each in turn are coupled to multiple NVM dies, as well as processing of host database operations such as insert, select, update, and delete. Each FM ASIC is architected to increase parity bits to 33.3% of NVM data, and process parity data with 14 LDPC's. By increasing the parity bits to 33.3%, BER is reduced, power consumption is reduced, and data throughput within the SSD is increased.

    Method for maximizing frequency while checking data integrity on a physical interface bus
    6.
    发明授权
    Method for maximizing frequency while checking data integrity on a physical interface bus 有权

    公开(公告)号：US10466920B2

    公开(公告)日：2019-11-05

    申请号：US15679468

    申请日：2017-08-17

    Applicant: Western Digital Technologies, Inc.

    Inventor： Yonatan Tzafrir ,  Mordekhay Zehavi ,  Mahmud Asfur

    IPC: G11C8/00 ,  G06F3/06 ,  G06K7/00

    Abstract: A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller performs a first operation on the memory through the memory interface at a first frequency associated with the host interface to determine a first data pattern. The controller performs a read operation on the memory through the memory interface at a second frequency to determine a second data pattern. The controller changes the first frequency by a predetermined amount until the first frequency is equal to a maximum operating frequency having an associated risk of a setup/hold violation that is below a predetermined probability.

    Method for maximizing power efficiency in memory interface block
    7.
    发明授权
    Method for maximizing power efficiency in memory interface block 有权

    公开(公告)号：US10446254B1

    公开(公告)日：2019-10-15

    申请号：US15970832

    申请日：2018-05-03

    Applicant: Western Digital Technologies, Inc.

    Inventor： Mordekhay Zehavi ,  Mahmud Asfur ,  Yonatan Tzafrir

    IPC: G11C29/50 ,  G06F11/07

    Abstract: A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller writes a first data test to a memory device through either the host interface or the memory interface at a first voltage level to determine a first write value. The controller reads the first data test written to the memory device through the same interface, either the host interface or the memory interface, at a second voltage level to determine a first read value. The controller then changes the second voltage to a third voltage based on a determination of whether the first read value is equal to the first write value to dynamically alter a working voltage level of the storage device in response to changing process, voltage, and temperature conditions.

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