摘要:
A system and method for providing an odometer verification for a vehicle. The method carried out by the system includes the steps of: (a) receiving authorization from a customer to periodically store odometer information obtained from the customer's vehicle; (b) configuring at least one processing device such that it automatically stores odometer readings and associated correlation parameter values for the vehicle; (c) receiving a request for an odometer verification; (d) analyzing the odometer readings and associated correlation parameter values in response to the request; (e) determining a verification result based on the analysis; and (f) sending the verification result to a recipient in response to the determination.
摘要:
A system and method for providing an odometer verification for a vehicle. The method carried out by the system includes the steps of: (a) receiving authorization from a customer to periodically store odometer information obtained from the customer's vehicle; (b) configuring at least one processing device such that it automatically stores odometer readings and associated correlation parameter values for the vehicle; (c) receiving a request for an odometer verification; (d) analyzing the odometer readings and associated correlation parameter values in response to the request; (e) determining a verification result based on the analysis; and (f) sending the verification result to a recipient in response to the determination.
摘要:
Systems and methods for odometer monitoring are disclosed herein. One example method includes storing an odometer value and a vehicle position in response to an initial triggering event, and determining a second odometer value and a second vehicle position in response to a subsequent triggering event. The odometer value is compared with the second odometer value to detect any odometer value change from the initial triggering event to the subsequent triggering event. The vehicle position is compared with the second vehicle position to detect any vehicle position change from the initial triggering event to the subsequent triggering event. From the comparisons, it is determined whether odometer tampering has occurred.
摘要:
Systems and methods for odometer monitoring are disclosed herein. One example method includes storing an odometer value and a vehicle position in response to an initial triggering event, and determining a second odometer value and a second vehicle position in response to a subsequent triggering event. The odometer value is compared with the second odometer value to detect any odometer value change from the initial triggering event to the subsequent triggering event. The vehicle position is compared with the second vehicle position to detect any vehicle position change from the initial triggering event to the subsequent triggering event. From the comparisons, it is determined whether odometer tampering has occurred.
摘要:
A speech-based system for assessing the psychological, physiological, or other characteristics of a test subject is described. The system includes a knowledge base that stores one or more speech models, where each speech model corresponds to a characteristic of a group of reference subjects. Signal processing circuitry, which may be implemented in hardware, software and/or firmware, compares the test speech parameters of a test subject with the speech models. In one embodiment, each speech model is represented by a statistical time-ordered series of frequency representations of the speech of the reference subjects. The speech model is independent of a priori knowledge of style parameters associated with the voice or speech. The system includes speech parameterization circuitry for generating the test parameters in response to the test subject's speech. This circuitry includes speech acquisition circuitry, which may be located remotely from the knowledge base. The system further includes output circuitry for outputting at least one indicator of a characteristic in response to the comparison performed by the signal processing circuitry. The characteristic may be time-varying, in which case the output circuitry outputs the characteristic in a time-varying manner. The output circuitry also may output a ranking of each output characteristic. In one embodiment, one or more characteristics may indicate the degree of sincerity of the test subject, where the degree of sincerity may vary with time. The system may also be employed to determine the effectiveness of treatment for a psychological or physiological disorder by comparing psychological or physiological characteristics, respectively, before and after treatment.
摘要:
A device is configured with components to enable debugging of the device's entry into and exit from a low power mode. The device includes: core logic, debug components, and a power management module (PMM). When the device exits a low power mode in which the states of the debug components are lost, the PMM prevents the core logic from resuming processing operations until the debug components have been re-configured to their prior states. The PMM either holds the core logic in reset or alternatively withholds power to the core logic. Reconfiguration of the debug components is initiated by a connected debugger, which can set one or more control and status (CS) register values within the device. The CS register values determine when the PMM prevents the core logic processing from resuming and when the PMM enables core logic processing to resume following the device's return from low power mode.
摘要:
A design-for-test (DFT) circuit for an integrated circuit (IC) for enabling accurate quiescent current testing. The IC includes a voltage supply pin, a ground pin and an internal voltage regulator coupled between the voltage supply and ground pins for providing an internal output voltage. The DFT circuit includes a voltage storage device which couples to the voltage regulator to temporarily maintain the internal output voltage when the voltage regulator is disabled. The mode control circuit detects a quiescent current test mode, disables the voltage regulator and decouples the voltage regulator from the voltage storage device when the quiescent current test mode is detected. The DFT circuit may include an enable circuit which generates a freeze signal when the quiescent current test mode is detected, and at least one switch which decouples the voltage regulator from the voltage storage node. The DFT circuit is particularly useful for low pin-count ICs.
摘要:
A regulator device includes a first valve member and a second valve member disposed within a housing of the device. The first valve member regulates the pressure of fluid exiting the device, and the second valve member is biased to a closed position and is opened by manipulation of an actuator. A sealing element is connected at the housing outlet and has a transverse cross-sectional dimension that decreases from an inlet of the sealing element to an outlet of the sealing element. In addition, a guard is provided that extends around a periphery of the actuator and includes a cut-out section to permit easy access to the actuator during use of the device.
摘要:
Among other things, an inkjet print head module includes inkjets from which ink drops are to be jetted during a series of jetting cycles. There is circuitry on the inkjet print head module to (a) form, from trimming information or other information that characterizes jetting waveforms to be applied to respective inkjets in respective jetting cycles, corresponding jetting waveforms and (b) apply the formed jetting waveforms to the respective inkjets in the respective jetting cycles.
摘要:
A device is configured with components to enable debugging of the device's entry into and exit from a low power mode. The device includes: core logic, debug components, and a power management module (PMM). When the device exits a low power mode in which the states of the debug components are lost, the PMM prevents the core logic from resuming processing operations until the debug components have been re-configured to their prior states. The PMM either holds the core logic in reset or alternatively withholds power to the core logic. Reconfiguration of the debug components is initiated by a connected debugger, which can set one or more control and status (CS) register values within the device. The CS register values determine when the PMM prevents the core logic processing from resuming and when the PMM enables core logic processing to resume following the device's return from low power mode.