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公开(公告)号：US07043390B2
公开(公告)日：2006-05-09
申请号：US11021965
申请日：2004-12-21
IPC分类号： G06F3/05
CPC分类号： G01R31/31907 , G01R31/31922
摘要： Method and apparatus for circuit testing with ring-connected test instrument modules. A system for controlling one or more test instruments to test one or more integrated circuits includes a master clock and a controller. The test instruments are connected to form a communication ring. The master clock is connected to each test instrument and provides a clock signal to the one or more test instruments. The controller is connected to the communication ring and is configured to align counters of test instruments to derive a common clock time value from the clock signal. The controller is further configured to generate and send data words into the communication ring to carry the data words to each test instrument. The data words includes at least one data word specifying a test event to be performed, a common clock time value, and at least one of the test instruments.
摘要翻译： 使用环形测试仪器模块进行电路测试的方法和装置。 用于控制一个或多个测试仪器以测试一个或多个集成电路的系统包括主时钟和控制器。 测试仪器连接形成一个通讯环。 主时钟连接到每个测试仪器，并向一个或多个测试仪器提供时钟信号。 控制器连接到通信环，并配置为对准测试仪器的计数器，以从时钟信号中导出公共时钟时间值。 该控制器还被配置为产生数据字并将其发送到通信环中，以将数据字携带到每个测试仪器。 数据字包括指定要执行的测试事件，公共时钟时间值和至少一个测试仪器的至少一个数据字。
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公开(公告)号：US07496467B2
公开(公告)日：2009-02-24
申请号：US11422114
申请日：2006-06-05
申请人： William A. Fritzsche
发明人： William A. Fritzsche
IPC分类号： G06F19/00
CPC分类号： G01R31/31907 , G01R31/31908 , G01R31/31912
摘要： An integrated circuit testing device, such as an ATE, configured with an architecture comprising a distinct software layer and a distinct hardware layer with an interface for tester abstraction providing a communication conduit between the software layer and the hardware layer. The software layer communicates in device under test terms whereas the hardware layer communicates in the terms of the testing apparatus. Various communication interface points are provided to the software and hardware layers, as well as the interface for tester abstraction.
摘要翻译： 诸如ATE的集成电路测试设备被配置为包括不同软件层的架构，以及具有用于测试器抽象的接口的不同硬件层，提供软件层和硬件层之间的通信管道。 软件层在测试条件下的设备中通信，而硬件层根据测试装置的方式进行通信。 提供各种通信接口点到软件和硬件层，以及用于测试人员抽象的接口。
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公开(公告)号：US07302358B2
公开(公告)日：2007-11-27
申请号：US11383972
申请日：2006-05-18
申请人： William A. Fritzsche
发明人： William A. Fritzsche
IPC分类号： G06F19/00
CPC分类号： G01R31/31907 , G01R31/31908 , G01R31/31912
摘要： An integrated circuit testing device, such as an ATE, configured with an architecture comprising a distinct software layer and a distinct hardware layer with an interface for tester abstraction providing a communication conduit between the software layer and the hardware layer. The software layer communicates in device under test terms whereas the hardware layer communicates in the terms of the testing apparatus. Various communication interface points are provided to the software and hardware layers, as well as the interface for tester abstraction.
摘要翻译： 诸如ATE的集成电路测试设备被配置为包括不同软件层的架构，以及具有用于测试器抽象的接口的不同硬件层，提供软件层和硬件层之间的通信管道。 软件层在测试条件下的设备中通信，而硬件层根据测试装置的方式进行通信。 提供各种通信接口点到软件和硬件层，以及用于测试人员抽象的接口。
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公开(公告)号：US07099791B2
公开(公告)日：2006-08-29
申请号：US10960532
申请日：2004-10-07
申请人： William A. Fritzsche
发明人： William A. Fritzsche
CPC分类号： G01R31/318371 , G01R31/31908 , G01R31/31919
摘要： A method for linking compiled pattern data and loading the data into tester hardware includes the steps of generating a composite object that includes a shared resource, determining a local shared resource specific to a test instrument that is associated with the shared resource in the composite object, assigning a local reconciled value or address to the local shared resource, and loading the local shared resource into the test instrument.
摘要翻译： 用于将编译的模式数据和将数据加载到测试器硬件中的方法包括以下步骤：生成包括共享资源的复合对象，确定与复合对象中的共享资源相关联的测试工具特有的本地共享资源， 将本地对帐的值或地址分配给本地共享资源，并将本地共享资源加载到测试仪器中。
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5.发明授权公开(公告)号：US06794861B2
公开(公告)日：2004-09-21
申请号：US10106280
申请日：2002-03-25
IPC分类号： G01R2702
CPC分类号： G01R35/005
摘要： Method and apparatus for calibrating timing accuracy during testing of integrated circuits. An ATE type (automatic test equipment) integrated circuit tester calibrates itself to reference blocks (dummy ICs) that have the same relevant dimensions as the integrated circuits to be tested and have fit into the test fixture. The number of reference blocks required is equal to the number of signal terminals on the integrated circuit to be tested subject to timing calibration where typically the number of signal terminals is less than the total number of signal terminals on the IC being tested and is typically a relatively small number, e.g., 9. This is useful in the case of high pin count integrated circuits where the pins are grouped into relatively small numbers of pins which are source synchronous. A signal trace electrically connects a different signal terminal to a common reference terminal on each reference block in the set. The reference blocks are then cycled through the tester apparatus as if they were an IC under test, resulting in timing calibration. This allows calibration for critical timing skew requirements for small groups of input/output pins on the IC under test.
摘要翻译： 在集成电路测试期间校准定时精度的方法和装置。 ATE型（自动测试设备）集成电路测试仪将其自身校准为具有与要测试的集成电路相同的相关尺寸并具有适合测试夹具的参考块（虚拟IC）。 所需的参考块的数量等于要进行定时校准的待测试集成电路上的信号端子的数量，其中信号端子的数量通常小于被测试的IC上的信号端子的总数，并且通常为 相对较小的数字，例如9.这在高引脚数集成电路的情况下是有用的，其中引脚被分组为相对较少数量的源同步的引脚。 信号迹线将不同的信号端子电连接到该组中每个参考块上的公共参考端子。 然后将参考块循环穿过测试仪器，好像它们是被测试的IC，从而进行定时校准。 这允许校准针对待测IC上的小组输入/输出引脚的关键定时偏移要求。
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公开(公告)号：US07107173B2
公开(公告)日：2006-09-12
申请号：US10888863
申请日：2004-07-09
申请人： William A. Fritzsche
发明人： William A. Fritzsche
IPC分类号： G06F19/00
CPC分类号： G01R31/31907 , G01R31/31908 , G01R31/31912
摘要： An integrated circuit testing device, such as an ATE, configured with an architecture comprising a distinct software layer and a distinct hardware layer with an interface for tester abstraction providing a communication conduit between the software layer and the hardware layer. The software layer communicates in device under test terms whereas the hardware layer communicates in the terms of the testing apparatus. Various communication interface points are provided to the software and hardware layers, as well as the interface for tester abstraction.
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公开(公告)号：US07370255B2
公开(公告)日：2008-05-06
申请号：US11049119
申请日：2005-02-01
CPC分类号： G01R31/31907 , G01R31/31922
摘要： Method and apparatus for circuit testing with ring-connected test instrument modules. A system for controlling one or more test instruments to test one or more integrated circuits includes a master clock and a controller. The test instruments are connected to form a communication ring. The master clock is connected to each test instrument and provides a clock signal to the one or more test instruments. The controller is connected to the communication ring and is configured to align counters of test instruments to derive a common clock time value from the clock signal. The controller is further configured to generate and send data words into the communication ring to carry the data words to each test instrument. The data words includes at least one data word specifying a test event to be performed, a common clock time value, and at least one of the test instruments.
摘要翻译： 使用环形测试仪器模块进行电路测试的方法和装置。 用于控制一个或多个测试仪器以测试一个或多个集成电路的系统包括主时钟和控制器。 测试仪器连接形成一个通讯环。 主时钟连接到每个测试仪器，并向一个或多个测试仪器提供时钟信号。 控制器连接到通信环，并配置为对准测试仪器的计数器，以从时钟信号中导出公共时钟时间值。 该控制器还被配置为产生数据字并将其发送到通信环中，以将数据字携带到每个测试仪器。 数据字包括指定要执行的测试事件，公共时钟时间值以及至少一个测试仪器的至少一个数据字。
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公开(公告)号：US06492797B1
公开(公告)日：2002-12-10
申请号：US09514708
申请日：2000-02-28
IPC分类号： G01R1132
CPC分类号： G01R31/31905 , G01R31/3191 , G01R35/005
摘要： A method and apparatus for calibrating tester timing accuracy during testing of integrated circuits. An ATE tester measures itself through reference blocks that have the same relevant dimensions as the integrated circuits to be tested. The number of reference blocks required is equal to the number of signal terminals on an integrated circuit to be tested being subject to timing calibration. A signal trace electrically connects a different signal terminal to a common reference terminal on each reference block. Each signal trace used should be closely matched both physically and electrically to the other signal traces used in the set of reference blocks, so that the electrical path length associated with each trace is nearly identical. To perform the timing calibration, the reference blocks may be mounted on a single fixture one at a time, or using multi-site fixtures, multiple reference blocks may be used in parallel. The fixture provides electrical connection of the reference block to the loadboard, and ultimately, the tester.
摘要翻译： 一种在集成电路测试期间校准测试仪定时精度的方法和装置。 ATE测试仪通过与要测试的集成电路具有相同尺寸的参考块来测量自身。 所需的参考块的数量等于要进行定时校准的待测试集成电路上的信号端子数。 信号迹线将不同的信号端子电连接到每个参考块上的公共参考端子。 所使用的每个信号迹线应该在物理和电气上与在该组参考块中使用的其它信号迹线紧密匹配，使得与每个迹线相关联的电路径长度几乎相同。 为了执行定时校准，参考块可以一次一个地安装在单个固定器上，或者使用多位置固定装置，可以并行使用多个参考块。 该夹具提供参考块与装载板的电连接，最终提供测试仪。
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