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公开(公告)号：US5696797A
公开(公告)日：1997-12-09
申请号：US279376
申请日：1994-07-22
IPC分类号： H04L27/00 , H04L27/233 , H04L27/06
CPC分类号： H04L27/2332 , H04L2027/003 , H04L2027/0057 , H04L2027/0095
摘要： An apparatus and accompanying method for demodulating with baseband Doppler frequency shift compensation. An RF section (20) down-converts received data communication signals (12) to baseband. A/D converters (24, 26) digitize I, Q quadrature baseband signal components. Phase (32) and frequency (50) tracking loops reside on a common digital ASIC substrate (28). A complex multiplier (30) rotates digitized baseband signals by a digitized oscillation signal, producing Doppler shift compensated signals. The phase tracking loop (32) estimates data and generates a pure phase error signal from which data modulation and Doppler shift compensation influences have been removed, which drives a frequency discriminator (52) that identifies either clockwise or counterclockwise phase rotation for each symbol (18). An integrator (54) combines identification results over a burst and a numerically controlled oscillator (56) adjusts the digitized oscillation signal frequency in a constant frequency step. This adjustment takes place once for each burst.
摘要翻译： 一种用基带多普勒频移补偿进行解调的装置及其附带方法。 RF部分（20）将接收的数据通信信号（12）下变频到基带。 A / D转换器（24,26）数字化I，Q正交基带信号分量。 相位（32）和频率（50）跟踪环路驻留在公共数字ASIC基板（28）上。 复数乘法器（30）通过数字化的振荡信号旋转数字化的基带信号，产生多普勒频移补偿信号。 相位跟踪环路（32）估计数据并产生一个纯相位误差信号，数据调制和多普勒频移补偿影响已从该相位误差信号中消除，驱动一个频率鉴别器（52），它识别每个符号（18）的顺时针或逆时针相位旋转 ）。 积分器（54）将突发的识别结果与数控振荡器（56）组合，以恒定频率步长调整数字化的振荡信号频率。 对于每个突发，这种调整发生一次。
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公开(公告)号：US5774508A
公开(公告)日：1998-06-30
申请号：US581979
申请日：1996-01-02
CPC分类号： H04L7/0334
摘要： In a data synchronizer a timing error estimator samples a received stream of digitized data symbols at the beginning, end, and a mid-point of a symbol period. These samples are used with a model that assumes that a data stream waveform should transition along a straight line between its values at optimum sampling instances, separated by the symbol period. Differences between a mid-symbol sample estimated using this straight line model and the actual mid-symbol sample are assumed to be due to a timing error. The timing error estimator performs computations on complex inputs and therefore is compatible with a wide variety of modulation types.
摘要翻译： 在数据同步器中，定时误差估计器在符号周期的开始，结束和中点对所接收的数字化数据符号流进行采样。 这些样本与模型一起使用，假定数据流波形应在最佳采样实例之间的直线之间沿直线转换，并以符号周期分隔。 假设使用该直线模型估计的中间符号样本与实际中间符号样本之间的差异被认为是由于定时误差引起的。 定时误差估计器对复杂输入进行计算，因此与各种调制类型兼容。
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3.发明授权Method and apparatus for adaptive filtering in a high interference environment 失效在高干扰环境下进行自适应滤波的方法和装置
公开(公告)号：US5703903A
公开(公告)日：1997-12-30
申请号：US509684
申请日：1995-07-31
CPC分类号： H04L25/03038 , H04L2025/03662
摘要： A method and apparatus for performing adaptive filtering in a high interference environment, such as for a radio, modem, or local area network. The adaptive filtering simultaneously provides interference excision while canceling resultant distortion in the signal caused by synthesizing the notch used to excise the interfering signal. An input signal (13) is pre-filtered (14) and the pre-filtered signal (15) is processed by a rejection filter (12) which combines weighted delayed versions of the pre-filtered signal (40, 42, 44, 46, 48, 50), weighted delayed versions of data decisions corresponding to the same delays as that used in the pre-filtered signal (60, 62, 64, 66, 68, 70), and a post filtered signal (27) to produce the filtered signal (19). The filtered signal (19) is processed by a data and coefficient estimator (18) to provide data decisions (25) and tap weight values (21, 23).
摘要翻译： 一种用于在诸如用于无线电，调制解调器或局域网的高干扰环境中执行自适应滤波的方法和装置。 自适应滤波同时提供干扰切除，同时消除由合成用于消除干扰信号的陷波引起的信号中的结果失真。 输入信号（13）被预滤波（14），并且预滤波信号（15）由拒绝滤波器（12）处理，该滤波器（12）将预滤波信号（40,42,44,46 ，48,50），对应于与预滤波信号（60,62,64,66,68,70）中使用的延迟相同的延迟的数据判定的加权延迟版本，以及后滤波信号（27），以产生 滤波信号（19）。 滤波信号（19）由数据和系数估计器（18）处理以提供数据判定（25）和抽头权重值（21,23）。
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公开(公告)号：US5694440A
公开(公告)日：1997-12-02
申请号：US582840
申请日：1996-01-02
CPC分类号： H03L7/095 , H04L7/0334
摘要： In a data synchronizer a timing error estimator samples a received data stream and generates a clock to provide optimal sampling of the data stream, and a lock detector monitors the clock and received data stream to provide an indication of whether optimal sampling has been achieved. The lock detector processes differences between delayed versions of the input which are sampled based upon the clock timing. These sampled differences are then processed by a non-linear circuit to provide a lock signal indication which, when compared to a predetermined threshold signal, is used to provide optimal sampling indication. The lock detector performs computations on real and complex inputs and therefore is compatible with a wide variety of modulation types. The lock detector can be implemented in either analog or digital circuits, making it applicable to a broad range of data synchronizer applications.
摘要翻译： 在数据同步器中，定时误差估计器对接收的数据流进行采样并产生时钟以提供数据流的最佳采样，并且锁定检测器监视时钟和接收的数据流以提供是否已经实现最佳采样的指示。 锁定检测器处理基于时钟定时采样的输入的延迟版本之间的差异。 然后，这些采样的差异由非线性电路处理，以提供锁定信号指示，当与预定的阈值信号相比时，其被用于提供最佳采样指示。 锁定检测器对实际和复杂输入进行计算，因此与各种调制类型兼容。 锁定检测器可以在模拟或数字电路中实现，使其适用于广泛的数据同步器应用。
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