公开(公告)号：US07401201B2

公开(公告)日：2008-07-15

申请号：US11413422

申请日：2006-04-28

申请人： William C. Moyer ,  Ray C. Marshall ,  Richard Soja

发明人： William C. Moyer ,  Ray C. Marshall ,  Richard Soja

IPC分类号： G06F12/00

CPC分类号： G06F12/1027

摘要： In a processor having an address translation table, a method includes providing a logical address and control signal. When the control signal has a first value, a first physical address is provided corresponding to the logical address, and when the control signal has a second value, a second physical address is provided. The first physical address and the second physical address are stored in at least one valid entry of the address translation table. In one case, the first physical address is stored in a first valid entry having a tag field which matches the logical address and the second physical address is stored in a second valid entry having a tag field which matches the logical address. Alternatively, the first physical address is stored in a first field of a first valid entry and the second physical address is stored in a second field of the first valid entry.

摘要翻译： 在具有地址转换表的处理器中，一种方法包括提供逻辑地址和控制信号。 当控制信号具有第一值时，对应于逻辑地址提供第一物理地址，并且当控制信号具有第二值时，提供第二物理地址。 第一物理地址和第二物理地址存储在地址转换表的至少一个有效条目中。 在一种情况下，第一物理地址存储在具有与逻辑地址匹配的标签字段的第一有效条目中，并且第二物理地址被存储在具有与逻辑地址匹配的标签字段的第二有效条目中。 或者，第一物理地址存储在第一有效条目的第一字段中，并且第二物理地址存储在第一有效条目的第二字段中。

公开(公告)号：US07447867B2

公开(公告)日：2008-11-04

申请号：US11413430

申请日：2006-04-28

申请人： Richard Soja ,  William C. Moyer ,  Ray C. Marshall

发明人： Richard Soja ,  William C. Moyer ,  Ray C. Marshall

IPC分类号： G06F12/00

CPC分类号： G06F12/1027 ,  G06F12/0292

摘要： A method includes providing an effective address, providing an address space identifier which identifies a currently executing process, providing a mapping modifier to form a modified address space identifier where the mapping modifier is based on at least one external signal generated outside the processor, using the effective address and the modified address space identifier to form a logical address, and providing a physical address corresponding to the logical address. When the effective address has a first effective address value, the address space identifier has a first address space identifier value, and the mapping modifier has a first mapping value, the physical address has a first physical address value. When the effective address has the first effective address value, the address space identifier has the first address space identifier value, and the mapping modifier has a second mapping value, the physical address has a second physical address value.

摘要翻译： 一种方法包括提供有效地址，提供标识当前执行过程的地址空间标识符，提供映射修饰符以形成修改的地址空间标识符，其中映射修饰符基于在处理器外部生成的至少一个外部信号，使用 有效地址和修改的地址空间标识符以形成逻辑地址，并提供对应于逻辑地址的物理地址。 当有效地址具有第一有效地址值时，地址空间标识符具有第一地址空间标识符值，并且映射修饰符具有第一映射值，物理地址具有第一物理地址值。 当有效地址具有第一有效地址值时，地址空间标识符具有第一地址空间标识符值，并且映射修饰符具有第二映射值，物理地址具有第二物理地址值。

公开(公告)号：US07870430B2

公开(公告)日：2011-01-11

申请号：US12040215

申请日：2008-02-29

申请人： Alistair P. Robertson ,  William C. Moyer ,  Ray C. Marshall

发明人： Alistair P. Robertson ,  William C. Moyer ,  Ray C. Marshall

IPC分类号： G06F11/00

CPC分类号： G06F11/3648 ,  G06F11/2236

摘要： A method includes providing an integrated circuit having a plurality of debug resources. The debug resources are usable exclusively for debug operations. The debug operations include operations directed by debug software executed by the integrated circuit and operations directed by external debug hardware which is external to the integrated circuit. The method further includes enabling availability of a first portion of the debug resources for use by the debug software, where a second portion of the debug resources are committed for exclusive use by the external debug hardware. The first portion is exclusive of the second portion. The method includes performing operations directed by the debug software using at least one debug resource of the first portion of the debug resources and operations directed by the external debug hardware using at least one debug resource of the second portion of the debug resources.

摘要翻译： 一种方法包括提供具有多个调试资源的集成电路。 调试资源专用于调试操作。 调试操作包括由集成电路执行的调试软件和由集成电路外部的外部调试硬件引导的操作所执行的操作。 该方法还包括使得调试资源的第一部分的可用性被调试软件使用，其中调试资源的第二部分被提交供外部调试硬件专用。 第一部分不包括第二部分。 该方法包括使用调试资源的第一部分的至少一个调试资源和外部调试硬件使用调试资源的第二部分的至少一个调试资源来执行的操作来执行由调试软件执行的操作。

公开(公告)号：US20090222692A1

公开(公告)日：2009-09-03

申请号：US12040215

申请日：2008-02-29

申请人： Alistair P. Robertson ,  William C. Moyer ,  Ray C. Marshall

发明人： Alistair P. Robertson ,  William C. Moyer ,  Ray C. Marshall

IPC分类号： G06F11/22

CPC分类号： G06F11/3648 ,  G06F11/2236

摘要： A method includes providing an integrated circuit having a plurality of debug resources. The debug resources are usable exclusively for debug operations. The debug operations include operations directed by debug software executed by the integrated circuit and operations directed by external debug hardware which is external to the integrated circuit. The method further includes enabling availability of a first portion of the debug resources for use by the debug software, where a second portion of the debug resources are committed for exclusive use by the external debug hardware. The first portion is exclusive of the second portion. The method includes performing operations directed by the debug software using at least one debug resource of the first portion of the debug resources and operations directed by the external debug hardware using at least one debug resource of the second portion of the debug resources.

摘要翻译： 一种方法包括提供具有多个调试资源的集成电路。 调试资源专用于调试操作。 调试操作包括由集成电路执行的调试软件和由集成电路外部的外部调试硬件引导的操作所执行的操作。 该方法还包括使得调试资源的第一部分的可用性被调试软件使用，其中调试资源的第二部分被提交供外部调试硬件专用。 第一部分不包括第二部分。 该方法包括使用调试资源的第一部分的至少一个调试资源和外部调试硬件使用调试资源的第二部分的至少一个调试资源来执行的操作来执行由调试软件执行的操作。

公开(公告)号：US10031773B2

公开(公告)日：2018-07-24

申请号：US14185005

申请日：2014-02-20

申请人： William C. Moyer

发明人： William C. Moyer

IPC分类号： G06F9/48

摘要： Task context information is transferred concurrently from a processor core to an accelerator and to a context memory. The accelerator performs an operation based on the task context information and the context memory saves the task context information. The order of transfer between the processor core is based upon a programmable indicator. During a context restore operation information is concurrently provided to data bus from both the accelerator and the processor core.

公开(公告)号：US09372723B2

公开(公告)日：2016-06-21

申请号：US14231784

申请日：2014-04-01

申请人： Zheng Xu ,  Tommi M. Jokinen ,  William C. Moyer

发明人： Zheng Xu ,  Tommi M. Jokinen ,  William C. Moyer

IPC分类号： G06F9/48

CPC分类号： G06F9/4843 ,  G06F9/461 ,  G06F9/48

摘要： A data processing system includes a processor core and ordering scope manager circuitry. The processor core sends an indication of a first ordering scope identifier for a current ordering scope a task currently being executed by the processor core and a second ordering scope identifier for a next-in-order ordering scope of the task. The ordering scope manager receives the indication the first and second ordering scope identifiers from processor core, and, provides a no task switch indicator to the processor core in response to determining that the first task is a first-in-transition-order task for the first ordering scope identifier and that processor core is authorized to execute the next-in-order ordering scope. The processor core transitions from executing in the current ordering scope to executing in the next-in-order ordering scope without performing task switch in response to the no task switch indicator being provided.

摘要翻译： 数据处理系统包括处理器核心和订购范围管理器电路。 处理器核心向当前订购范围发送当前由处理器核心执行的任务的第一订购范围标识符和用于任务的下一个订购范围的第二订购范围标识符的指示。 订购范围管理器从处理器核心接收第一和第二订购范围标识符的指示，并且响应于确定第一任务是第一个转换顺序任务，向处理器核心提供无任务切换指示符 第一个订购范围标识符，该处理器核心被授权执行下一个订购范围。 处理器核心从当前订购范围内的执行转变为按顺序排序范围执行，而不响应于提供无任务切换指示器而执行任务切换。

公开(公告)号：US20160098313A1

公开(公告)日：2016-04-07

申请号：US14504702

申请日：2014-10-02

申请人： William C. Moyer

发明人： William C. Moyer

IPC分类号： G06F11/07 ,  G06F9/50

CPC分类号： G06F11/0757 ,  G06F11/0724

摘要： Each task assigned to a core can be considered an “active” task. Sequential strobe signals of a watchdog signal can be spaced apart in time by a certain duration. The duration between strobe signals is longer than the expected duration of an active task. By knowing that all tasks being monitored are expected to execute within an expected amount of time, the duration between the strobe signals can be set to be longer than that expected amount of time. If a task has not transitioned to inactive by a next strobe, a watchdog error has occurred.

摘要翻译： 分配给核心的每个任务可以被认为是一个“主动”任务。 看门狗信号的顺序选通信号可以在时间上间隔一段持续时间。 选通信号之间的持续时间长于活动任务的预期持续时间。 通过知道所有被监视的任务预期在预期的时间内执行，选通信号之间的持续时间可以被设置为比预期的时间长。 如果任务没有被下一个选通转换为非活动状态，则发生看门狗错误。

公开(公告)号：US09268527B2

公开(公告)日：2016-02-23

申请号：US13841630

申请日：2013-03-15

申请人： William C. Moyer

发明人： William C. Moyer

IPC分类号： G06F7/483 ,  G06F7/499

CPC分类号： G06F7/483 ,  G06F7/49905

摘要： A floating point value can represent a number or something that is not a number (NaN). A floating point value that is a NaN having data field that stores information, such as a propagation count that indicates the number of times a NaN value has been propagated through instructions. A NaN evaluation instruction can determine whether one or more operands is a NaN operand of a particular type, and if so can generate a result that is a NaN of a different type. An exception can be generated based upon the NaN of the different type being provided as a resultant.

摘要翻译： 浮点值可以表示数字或不是数字（NaN）的数据。 具有存储信息的数据字段的NaN的浮点值，例如表示通过指令传播NaN值的次数的传播计数。 NaN评估指令可以确定一个或多个操作数是否是特定类型的NaN操作数，如果可以生成作为不同类型的NaN的结果。 可以基于作为结果提供的不同类型的NaN产生异常。

公开(公告)号：US20150277973A1

公开(公告)日：2015-10-01

申请号：US14231789

申请日：2014-04-01

申请人： Zheng Xu ,  Tommi M. Jokinen ,  William C. Moyer

发明人： Zheng Xu ,  Tommi M. Jokinen ,  William C. Moyer

IPC分类号： G06F9/48

CPC分类号： G06F9/4843 ,  G06F9/461 ,  G06F9/48

摘要： A data processing system includes a processor core and a hardware module. The processor core performs tasks on data packets. The hardware module stores a first ordering scope identifier at a first storage location of the ordering scope manager. The first ordering scope identifier indicates a first ordering scope that a first task is operating in. The ordering scope manager increments the first ordering scope identifier to create a new ordering scope identifier. In response to determining that the processor core is authorized to transition the first task from the first ordering scope to a second ordering scope associated with the new ordering scope identifier, the ordering scope manager provides hint information to the processor core. The processor core transitions from the first ordering scope to the second ordering scope without completing a task switch in response to the hint information.

摘要翻译： 数据处理系统包括处理器核心和硬件模块。 处理器内核在数据包上执行任务。 硬件模块在订购范围管理器的第一存储位置处存储第一订购范围标识符。 第一个订购范围标识符指示第一个任务正在操作的第一个订购范围。订购范围管理器增加第一个订购范围标识符以创建新的订购范围标识符。 响应于确定处理器核被授权将第一任务从第一排序范围转换到与新排序范围标识符相关联的第二排序范围，订购范围管理器向处理器核提供提示信息。 处理器核心从第一订购范围转换到第二订购范围，而不响应于提示信息完成任务切换。

公开(公告)号：US09104403B2

公开(公告)日：2015-08-11

申请号：US12858599

申请日：2010-08-18

申请人： Gary R. Morrison ,  William C. Moyer

发明人： Gary R. Morrison ,  William C. Moyer

IPC分类号： G06F15/00 ,  G06F9/30 ,  G06F9/40 ,  G06F11/14 ,  G06F11/16

CPC分类号： G06F9/30145 ,  G06F11/1405 ,  G06F11/1479 ,  G06F11/1497 ,  G06F11/1629

摘要： A method includes: decoding an instruction a first time to obtain a first decoded instruction; decoding the instruction a second time to obtain a second decoded instruction; comparing at least a portion of the first decoded instruction to at least a portion of the second decoded instruction; and when the at least a portion of the first decoded instruction matches the at least a portion of the second decoded instruction, executing the instruction.

摘要翻译： 一种方法包括：第一次解码指令以获得第一解码指令; 第二次对指令进行解码以获得第二解码指令; 将所述第一解码指令的至少一部分与所述第二解码指令的至少一部分进行比较; 并且当所述第一解码指令的至少一部分与所述第二解码指令的所述至少一部分匹配时，执行所述指令。