利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

5 条记录 (耗时 0.029 秒)

    Method and system for implementing remstat protocol under inclusion and non-inclusion of L1 data in L2 cache to prevent read-read deadlock
    3.
    发明授权
    Method and system for implementing remstat protocol under inclusion and non-inclusion of L1 data in L2 cache to prevent read-read deadlock 失效
    在L2缓存中包含和不包含L1数据的实现remstat协议的方法和系统，以防止读取死锁

    公开(公告)号：US06587930B1

    公开(公告)日：2003-07-01

    申请号：US09404400

    申请日：1999-09-23

    申请人： Sanjay Raghunath Deshpande ,  Peter Steven Lenk ,  Michael John Mayfield

    发明人： Sanjay Raghunath Deshpande ,  Peter Steven Lenk ,  Michael John Mayfield

    IPC分类号： G06F1200

    CPC分类号： G06F12/0811 ,  G06F12/0833

    摘要： A distributed system structure for a large-way, multi-bus, multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives commands from a master device, communicates with a master device as another master device or as a slave device, and queues commands received from a master device. The system allows for the implementation of a bus protocol that reports the state of a cache line to a master device along with the first beat of data delivery for a cacheable coherent Read. Since the achievement of coherency is distributed in time and space, the issue of data integrity is addressed through a variety of actions. In one implementation, the node controller helps to maintain cache coherency for commands by blocking a master device from receiving certain transactions so as to prevent Read-Read deadlocks. In another implementation, the master devices use a bus protocol that prevents Read-Read deadlocks in a distributed, multi-bus, multiprocessor system.

    摘要翻译： 提供了一种使用基于总线的高速缓存相干协议的大容量多总线多处理器系统的分布式系统结构。 分布式系统结构包含地址交换机，多个存储器子系统以及被组织成由节点控制器支持的一组节点的多个主设备，处理器，I / O代理或相干存储器适配器。 节点控制器从主设备接收命令，与主设备作为另一个主设备或从设备通信，并对从主设备接收的命令进行排队。 该系统允许执行总线协议，该总线协议将高速缓存行的状态与可高速缓存的相干读取的第一个数据传送节点一起报告给主设备。 由于实现一致性是在时间和空间上分配的，所以数据完整性的问题通过各种各样的动作来解决。 在一个实现中，节点控制器有助于通过阻止主设备接收某些事务来保持命令的高速缓存一致性，从而防止读取 - 读取死锁。 在另一实现中，主设备使用总线协议来防止分布式多总线多处理器系统中的读 - 读死锁。

    Ticket mechanism for sharing computer resources
    4.
    发明授权
    Ticket mechanism for sharing computer resources 失效
    共享计算机资源的票务机制

    公开(公告)号：US07904612B2

    公开(公告)日：2011-03-08

    申请号：US10887438

    申请日：2004-07-08

    申请人： Peter Steven Lenk

    发明人： Peter Steven Lenk

    IPC分类号： G06F13/14 ,  G06F9/50

    CPC分类号： G06F9/52

    摘要： Improved administering of shared resources in a computer system. In a preferred embodiment, transaction throughput is improved and potential starvation eliminated by a ticket mechanism. The ticket mechanism provides a wait counter and a service counter. When a requested transaction fails, a wait counter is incremented and a wait value is sent to the requesting transaction source. As transactions are completed at the resource, the service counter is incremented and its value broadcast to transaction sources sharing that resource. When a source holds a wait count value that equals the service count value, the source can retry the transaction successfully.

    摘要翻译： 改进在计算机系统中管理共享资源。 在一个优选实施例中，交易吞吐量得到改善，故障机制消除了潜在的饥饿。 机票机制提供等待计数器和服务计数器。 当请求的事务失败时，等待计数器递增，并且等待值被发送到请求的事务源。 随着事务在资源中完成，服务计数器递增，其值广播到共享该资源的事务源。 当源保持等于服务计数值的等待计数值时，源可以成功重试事务。

    Method and system for rapid line ownership transfer for multiprocessor updates
    5.
    发明授权
    Method and system for rapid line ownership transfer for multiprocessor updates 失效
    用于多处理器更新的快速线路所有权转移的方法和系统

    公开(公告)号：US6098156A

    公开(公告)日：2000-08-01

    申请号：US898323

    申请日：1997-07-22

    申请人： Peter Steven Lenk

    发明人： Peter Steven Lenk

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0831 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087

    摘要： A method and system according to the present invention of accessing data in a multiprocessor system including a plurality of processors and a memory, wherein the memory includes a plurality of memory locations, and wherein at least a first processor and a second processor each include a reservation indicator and a cache, each cache having a plurality of cache memory locations corresponding to the memory locations. The method and system comprises providing a Load And Reserve request from the first processor for at least one of the plurality of memory locations and determining whether the second processor includes at least one of the plurality of cache memory locations corresponding with the at least one of the memory locations; determining whether the second processor's reservation indicator is set, this determination being in response the second processor including the at least one of the cache memory locations corresponding with the at least one of the memory locations. The method and system also provides a state indicating that the at least one of the cache memory locations of the second processor corresponding to the at least one of the memory locations is invalid, responsive to the reservation indicator not being set.

    摘要翻译： 根据本发明的在包括多个处理器和存储器的多处理器系统中访问数据的方法和系统，其中所述存储器包括多个存储器位置，并且其中至少第一处理器和第二处理器各自包括预留 指示符和高速缓存，每个缓存具有对应于存储器位置的多个高速缓冲存储器位置。 所述方法和系统包括从所述第一处理器为所述多个存储器位置中的至少一个提供加载和保留请求，并且确定所述第二处理器是否包括与所述多个存储器位置中的至少一个相对应的所述多个高速缓冲存储器位置中的至少一个 记忆位置; 确定是否设置了第二处理器的预约指示符，该确定响应于第二处理器，其包括对应于存储器位置中的至少一个的高速缓冲存储器位置中的至少一个。 所述方法和系统还提供一个状态，其指示对应于所述至少一个所述存储器位置的所述第二处理器的所述高速缓冲存储器位置中的至少一个响应于所述预约指示符未被设置而无效。