公开(公告)号：US07707384B1

公开(公告)日：2010-04-27

申请号：US11745067

申请日：2007-05-07

申请人： William J. Dally ,  Scott W. Rixner

发明人： William J. Dally ,  Scott W. Rixner

IPC分类号： G06F12/00

CPC分类号： G11C8/04

摘要： A memory processing approach involves implementation of memory status-driven access. According to an example embodiment, addresses received at an address buffer are processed for access to a memory relative to an active location in the memory. Addresses corresponding to an active location in the memory array are processed prior to addresses that do not correspond to an active location. Data is read from the memory to a read buffer and ordered in a manner commensurate with the order of received addresses at the address buffer (e.g., thus facilitating access to the memory in an order different from that received at the address buffer while maintaining the order from the read buffer).

摘要翻译： 内存处理方法涉及实现内存状态驱动的访问。 根据示例实施例，处理在地址缓冲器处接收的地址，以相对于存储器中的活动位置访问存储器。 对应于存储器阵列中的活动位置的地址在不对应于活动位置的地址之前被处理。 将数据从存储器读取到读缓冲器，并以与地址缓冲器处的接收地址顺序相称的方式进行排序（例如，因此有助于以与地址缓冲器接收的顺序不同的顺序访问存储器，同时保持顺序 从读缓冲区）。

公开(公告)号：US07216214B2

公开(公告)日：2007-05-08

申请号：US11434392

申请日：2006-05-15

申请人： William J. Dally ,  Scott W. Rixner

发明人： William J. Dally ,  Scott W. Rixner

IPC分类号： G06F12/00

CPC分类号： G11C8/04 ,  G11C7/1006 ,  G11C11/408

摘要： A memory processing approach involves implementation of memory status-driven access. According to an example embodiment, addresses received at an address buffer are processed for access to a memory relative to an active location in the memory. Addresses corresponding to an active location in the memory array are processed prior to addresses that do not correspond to an active location. Data is read from the memory to a read buffer and ordered in a manner commensurate with the order of received addresses at the address buffer (e.g., thus facilitating access to the memory in an order different from that received at the address buffer while maintaining the order from the read buffer).

摘要翻译： 内存处理方法涉及实现内存状态驱动的访问。 根据示例实施例，处理在地址缓冲器处接收的地址，以相对于存储器中的活动位置访问存储器。 对应于存储器阵列中的活动位置的地址在不对应于活动位置的地址之前被处理。 将数据从存储器读取到读缓冲器，并以与地址缓冲器处的接收地址顺序相称的方式进行排序（例如，因此有助于以与地址缓冲器接收的顺序不同的顺序访问存储器，同时保持顺序 从读缓冲区）。

公开(公告)号：US07047391B2

公开(公告)日：2006-05-16

申请号：US11019979

申请日：2004-12-21

申请人： William J. Dally ,  Scott W. Rixner

发明人： William J. Dally ,  Scott W. Rixner

IPC分类号： G06F12/00

CPC分类号： G11C8/04 ,  G11C7/1006 ,  G11C11/408

摘要： A memory processing approach involves implementation of memory status-driven access. According to an example embodiment, addresses received at an address buffer are processed for access to a memory relative to an active location in the memory. Addresses corresponding to an active location in the memory array are processed prior to addresses that do not correspond to an active location. Data is read from the memory to a read buffer and ordered in a manner commensurate with the order of received addresses at the address buffer (e.g., thus facilitating access to the memory in an order different from that received at the address buffer while maintaining the order from the read buffer).

摘要翻译： 内存处理方法涉及实现内存状态驱动的访问。 根据示例实施例，处理在地址缓冲器处接收的地址，以相对于存储器中的活动位置访问存储器。 对应于存储器阵列中的活动位置的地址在不对应于活动位置的地址之前被处理。 将数据从存储器读取到读缓冲器，并以与地址缓冲器处的接收地址顺序相称的方式进行排序（例如，因此有助于以与地址缓冲器接收的顺序不同的顺序访问存储器，同时保持顺序 从读缓冲区）。

公开(公告)号：US08674768B2

公开(公告)日：2014-03-18

申请号：US13352221

申请日：2012-01-17

申请人： William J. Dally ,  John W. Poulton

发明人： William J. Dally ,  John W. Poulton

IPC分类号： H03G3/10

CPC分类号： H03G3/3036 ,  H03G3/3052 ,  H03K2005/00039

摘要： An integrated circuit receiver includes a first channel comprising an amplifier responsive to a first gain control value in a first mode to receive an input signal and generate a first amplified signal having a transition rate. Detection circuitry in the first channel detects transitions in the first amplified signal in accordance with a detected transition rate. The detected transition rate is based on the first gain control value. Gain control logic adjusts the first gain control value based on a desired detected transition rate. The gain control logic generates a second gain control value for use during a second mode. The second gain control value being based on the first gain control value.

摘要翻译： 集成电路接收器包括第一通道，其包括响应于第一模式中的第一增益控制值的放大器，以接收输入信号并产生具有转变速率的第一放大信号。 第一通道中的检测电路根据检测到的转换速率来检测第一放大信号中的转换。 所检测的转变速率基于第一增益控制值。 增益控制逻辑基于期望的检测到的转变速率来调整第一增益控制值。 增益控制逻辑产生在第二模式期间使用的第二增益控制值。 第二增益控制值基于第一增益控制值。

公开(公告)号：US08555035B1

公开(公告)日：2013-10-08

申请号：US12831953

申请日：2010-07-07

申请人： Anjul Patney ,  William J. Dally

发明人： Anjul Patney ,  William J. Dally

IPC分类号： G06F9/44

CPC分类号： G06F8/441

摘要： One embodiment of the present invention sets forth a technique for using a multi-bank register file that reduces the size of or eliminates a switch and/or staging registers that are used to gather input operands for instructions. Each function unit input may be directly connected to one bank of the multi-bank register file with neither a switch nor a staging register. A compiler or register allocation unit ensures that the register file accesses for each instruction are conflict-free (no instruction can access the same bank more than once in the same cycle). The compiler or register allocation unit may also ensure that the register file accesses for each instruction are also aligned (each input of a function unit can only come from the bank connected to that input).

摘要翻译： 本发明的一个实施例提出了一种使用减少用于收集用于指令的输入操作数的开关和/或分段寄存器的大小或消除的多存储体寄存器堆的技术。 每个功能单元输入可以直接连接到多存储区寄存器文件的一行，既不带有开关也不是暂存寄存器。 编译器或寄存器分配单元确保每个指令的寄存器文件访问是无冲突的（没有指令可以在同一周期内多次访问同一个存储体）。 编译器或寄存器分配单元还可以确保每个指令的寄存器文件访问也被对齐（功能单元的每个输入只能来自连接到该输入的存储体）。

公开(公告)号：US08487681B2

公开(公告)日：2013-07-16

申请号：US13033426

申请日：2011-02-23

申请人： William J. Dally ,  Jonah M. Alben ,  John W. Poulton ,  G E (Francis) Yang

发明人： William J. Dally ,  Jonah M. Alben ,  John W. Poulton ,  G E (Francis) Yang

IPC分类号： H03K3/356

CPC分类号： H03K3/36 ,  H03K3/012 ,  H03K3/356121

摘要： One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a dual-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The dual-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. One of the clock signals may be a low-frequency “keeper clock” that toggles less frequently than the other two clock signal that is input to two transistor gates. The output signal Q is set or reset at the rising clock edge using separate trigger sub-circuits. Either the set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.

公开(公告)号：US08259841B2

公开(公告)日：2012-09-04

申请号：US13027893

申请日：2011-02-15

申请人： William J. Dally

发明人： William J. Dally

IPC分类号： H04L27/04 ,  H04L25/03 ,  H04L27/00 ,  H03K5/156

CPC分类号： H04L25/03019 ,  H04B1/0483 ,  H04B1/1081 ,  H04B1/16 ,  H04B3/04 ,  H04L1/0042 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/03025 ,  H04L25/03343 ,  H04L25/03878 ,  H04L25/03885 ,  H04L27/01

摘要： An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer.

公开(公告)号：US08238470B2

公开(公告)日：2012-08-07

申请号：US13090507

申请日：2011-04-20

申请人： William J. Dally

发明人： William J. Dally

IPC分类号： H04L27/04 ,  H04L25/03 ,  H04L27/00 ,  H03K5/156

CPC分类号： H04L25/03019 ,  H04B1/0483 ,  H04B1/1081 ,  H04B1/16 ,  H04B3/04 ,  H04L1/0042 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/03025 ,  H04L25/03343 ,  H04L25/03878 ,  H04L25/03885 ,  H04L27/01

摘要： An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer.

公开(公告)号：US08228930B1

公开(公告)日：2012-07-24

申请号：US11445934

申请日：2006-06-02

申请人： John J. Kim ,  William J. Dally

发明人： John J. Kim ,  William J. Dally

IPC分类号： H04L12/56

CPC分类号： H04L12/56 ,  H04L49/25

摘要： Interconnection router arrangements are implemented using a variety of arrangements and methods. Using one such arrangement, an interconnection network router arrangement sends data units between a set of router inputs and a set of router outputs. The interconnection network router arrangement includes a sub-switch that is capable of selectively transferring a data unit from an array of sub-switch inputs to an array of sub-switch outputs. The sub-switch has a memory circuit for storing the data unit before the data unit is transferred to a sub-switch output and a memory circuit for storing the data unit after the data unit is transferred from the sub-switch inputs and before the data unit is sent to a router output.

摘要翻译： 互连路由器布置使用各种布置和方法来实现。 使用一种这样的布置，互连网络路由器布置在一组路由器输入和一组路由器输出之间发送数据单元。 互连网络路由器布置包括子交换机，其能够选择性地将数据单元从子开关输入阵列传送到子开关输出阵列。 子开关具有用于在将数据单元传送到副开关输出之前存储数据单元的存储电路和用于在数据单元从子开关输入传送之后并在数据之前存储数据单元的存储电路 单元发送到路由器输出。

公开(公告)号：US08102212B2

公开(公告)日：2012-01-24

申请号：US12840150

申请日：2010-07-20

申请人： William J. Dally ,  John W. Poulton

发明人： William J. Dally ,  John W. Poulton

IPC分类号： H03G3/10

CPC分类号： H03G3/3036 ,  H03G3/3052 ,  H03K2005/00039

摘要： An integrated circuit receiver includes a first channel comprising an amplifier responsive to a first gain control value in a first mode to receive an input signal and generate a first amplified signal having a transition rate. Detection circuitry in the first channel detects transitions in the first amplified signal in accordance with a detected transition rate. The detected transition rate is based on the first gain control value. Gain control logic adjusts the first gain control value based on a desired detected transition rate. The gain control logic generates a second gain control value for use during a second mode. The second gain control value being based on the first gain control value.

摘要翻译： 集成电路接收器包括第一通道，其包括响应于第一模式中的第一增益控制值的放大器，以接收输入信号并产生具有转变速率的第一放大信号。 第一通道中的检测电路根据检测到的转换速率来检测第一放大信号中的转换。 所检测的转变速率基于第一增益控制值。 增益控制逻辑基于期望的检测到的转变速率来调整第一增益控制值。 增益控制逻辑产生在第二模式期间使用的第二增益控制值。 第二增益控制值基于第一增益控制值。