公开(公告)号：US6108721A

公开(公告)日：2000-08-22

申请号：US107008

申请日：1998-06-29

申请人： William R. Bryg ,  Monish S. Shah ,  Thomas V. Spencer

发明人： William R. Bryg ,  Monish S. Shah ,  Thomas V. Spencer

IPC分类号： G06F12/08 ,  G06F13/12 ,  G06F13/28 ,  G06F13/38 ,  G06F13/00

CPC分类号： G06F13/122 ,  G06F12/0835 ,  G06F13/28

摘要： In a method and apparatus that ensures data consistency between an I/O channel and a processor, system software issues an instruction which causes the issuance of a transaction when notification of a DMA completion is received. The transaction instructs the I/O channel to enforce coherency and then responds back only after coherency has been ensured. Specifically, a DMA.sub.-- SYNC transaction is broadcast to all I/O channels in the system. Responsive thereto, each I/O channel writes back to memory any modified lines in its cache that might contain DMA data for a DMA sequence that was reported by the system as completed. The I/O channels have a reporting means to indicate when this transaction is completed, so that the DMA.sub.-- SYNC transaction does not have to complete in pipeline order. Thus, the I/O channel can issue new transactions before responding to the DMA.sub.-- SYNC transaction.

摘要翻译： 在确保I / O通道与处理器之间的数据一致性的方法和装置中，当接收到DMA完成通知时，系统软件发出导致事务发生的指令。 事务指示I / O通道强制执行一致性，然后仅在确保一致性后才响应。 具体来说，DMA-SYNC事务被广播到系统中的所有I / O通道。 响应于此，每个I / O通道将其缓存中的任何修改的行写回存储器，该行可能包含系统报告的完成的DMA序列的DMA数据。 I / O通道具有报告方式来指示此事务何时完成，以便DMA-SYNC事务不必以流水线顺序完成。 因此，在响应DMA-SYNC事务之前，I / O通道可以发出新的事务。

公开(公告)号：US5557756A

公开(公告)日：1996-09-17

申请号：US331312

申请日：1994-10-28

申请人： Thomas V. Spencer

发明人： Thomas V. Spencer

IPC分类号： G06F13/37 ,  G06F13/368

CPC分类号： G06F13/37

摘要： A bus arbitration circuit, having a state machine which receives a processor request signal, a request signal from each of a group of internal input/output devices, and an external device request signal. The state machine sends a processor grant signal, a grant signal to one of the internal devices, or a grant signal to the external device, as each of the devices receives control of the bus. The circuit has a signal inverter connected to the processor request signal and another signal inverter connected to the processor grant signal. A control signal controls whether or not the inverters invert the signals. When multiple arbitration circuits are cascaded, the processor request and grant signals are not inverted for the primary bus arbitration circuit, but the request and grant signals are inverted for all secondary bus arbitration circuits.

摘要翻译： 总线仲裁电路，具有接收处理器请求信号的状态机，来自一组内部输入/输出设备中的每一个的请求信号和外部设备请求信号。 由于每个设备接收总线的控制，状态机向外部设备发送处理器许可信号，授权信号到内部设备之一或授权信号。 电路具有连接到处理器请求信号的信号反相器和连接到处理器授权信号的另一信号反相器。 控制信号控制逆变器是否反转信号。 当多个仲裁电路级联时，对于主总线仲裁电路，处理器请求和授权信号不被反转，但是对于所有辅助总线仲裁电路，请求和授权信号被反相。

公开(公告)号：US06931497B2

公开(公告)日：2005-08-16

申请号：US10340078

申请日：2003-01-09

申请人： Shawn Adam Clayton ,  Shaun Andrew McMaster ,  Thomas V. Spencer

发明人： Shawn Adam Clayton ,  Shaun Andrew McMaster ,  Thomas V. Spencer

IPC分类号： G06F20060101 ,  G06F9/50 ,  G06F12/00

CPC分类号： G06F9/5016

摘要： A method includes receiving a first buffer allocation command from a first processor, the allocation command including a register address associated with a pool of buffers in a shared memory, determining whether a buffer is available in the buffer pool based upon a buffer index corresponding to a free buffer, and if a buffer is determined available allocating the buffer to the first processor.

摘要翻译： 一种方法包括从第一处理器接收第一缓冲器分配命令，所述分配命令包括与共享存储器中的缓冲器池相关联的寄存器地址，基于与缓冲器索引对应的缓冲器索引来确定缓冲器池中是否可用缓冲器 并且如果缓冲器被确定可用，则将缓冲器分配给第一处理器。

公开(公告)号：US5687395A

公开(公告)日：1997-11-11

申请号：US330478

申请日：1994-10-28

申请人： Thomas V. Spencer

发明人： Thomas V. Spencer

IPC分类号： G06F3/06 ,  G06F13/14

CPC分类号： G06F3/0601 ,  G06F2003/0691

摘要： A system for transferring data between main memory and an input/output device in a computer system, where device driver software stores an address of a circular buffer into the device and then the device automatically transfers data to or from the buffer. The system reduces complexity within the device by always starting the circular buffer on a page boundary, and allowing the circular buffer to be only one page long. Each time the buffer address passes either zero or half the buffer size, the system interrupts the processor to allow the driver software to transfer, to a hard disk or other area of memory, the contents of the half of the buffer that was just processed. The system further reduces complexity by transferring only eight bits of data into each word of the buffer within memory, therefore avoiding the complexity of byte packing.

摘要翻译： 一种用于在计算机系统中的主存储器和输入/输出设备之间传送数据的系统，其中设备驱动器软件将循环缓冲器的地址存储到设备中，然后该设备自动将数据传送到缓冲器或从缓冲器传送数据。 该系统通过始终在页面边界上启动循环缓冲区来降低设备内的复杂性，并允许循环缓冲区只有一页长。 每次缓冲区地址通过缓冲区大小的零或一半时，系统会中断处理器，以允许驱动程序软件将刚被处理的缓冲区的一半内容传输到硬盘或其他存储区域。 该系统通过仅将8位数据传送到存储器内的缓冲器的每个字进一步降低了复杂度，因此避免了字节打包的复杂性。

公开(公告)号：US20220137844A1

公开(公告)日：2022-05-05

申请号：US17515021

申请日：2021-10-29

申请人： Ryan J. Goss ,  David W. Claude ,  Daniel J. Benjamin ,  Thomas V. Spencer ,  Matthew B. Lovell

发明人： Ryan J. Goss ,  David W. Claude ,  Daniel J. Benjamin ,  Thomas V. Spencer ,  Matthew B. Lovell

IPC分类号： G06F3/06

摘要： A system can log data access activity to a memory array with a metadata module while the memory array is logically divided into multiple namespaces. A workload can be determined for each namespace by the metadata module and a metadata strategy can be created with the metadata module in view of the respective namespace workloads. A first metadata and second metadata may be generated for respective first and second user-generated data for storage into a first namespace of the multiple namespaces. The first metadata can be compressed with a compression level prescribed by the metadata strategy in response to a detected or predicted workload to the first namespace before the first metadata, second metadata, first user-generated data, and second user-generated data are each stored in the first namespace.

公开(公告)号：US06823439B2

公开(公告)日：2004-11-23

申请号：US10288616

申请日：2002-11-04

申请人： Thomas V. Spencer

发明人： Thomas V. Spencer

IPC分类号： G06F1200

CPC分类号： G06F11/3476

摘要： A method includes storing a plurality of system status messages of a specified size, and transmitting the status messages as a combined status message of a size larger than said specified size to an external device. In one aspect, the system status messages may have sizes that are less than the width of a bus, and said transmitting the combined status message includes transmitting the combined status message having a width equal to a width of the bus.

摘要翻译： 一种方法包括存储指定大小的多个系统状态消息，并将状态消息作为大于所述指定大小的组合状态消息发送到外部设备。 在一个方面，系统状态消息可以具有小于总线宽度的尺寸，并且所述发送组合状态消息包括发送具有等于总线宽度的宽度的组合状态消息。

公开(公告)号：US06772295B2

公开(公告)日：2004-08-03

申请号：US10322222

申请日：2002-12-17

申请人： Thomas V. Spencer ,  Robert J. Horning

发明人： Thomas V. Spencer ,  Robert J. Horning

IPC分类号： G06F1200

CPC分类号： G06F12/0875 ,  G06F12/0862 ,  G06F2212/6028

摘要： The present invention is generally directed to a system and method for fetching data from system memory to a device in communication with the system over a PCI bus, via an I/O cache. Broadly, the present invention may be viewed as a novel way to communicate certain fetching hints; namely, hints that specify certain qualities about the data that is to be fetched from the system memory. In operation, the I/O cache may use such hints to more effectively manage the data that passes through it. As simply one example, if, based upon the hints, the controller for the I/O cache knew (or assumed) that the data being fetched was ATM data, then it would also know (based upon the nature of ATM data) that precisely a forty-eight byte data payload was to be sent to the requesting device, and the I/O cache could pre-fetch precisely this amount of data (typically one or two cache lines). In accordance with one-aspect of the invention, such a system includes an input/output (I/O) cache memory interposed between the system memory and the PCI bus, wherein the cache memory has internal memory space in the form of a plurality of data lines within the cache memory. The system further includes a plurality of registers for each PCI master that are configured to define fetching criteria. Finally, the system includes a register selector that is configured to select an active register among the plurality of registers, wherein fetching criteria for the device is specified by the active register.

摘要翻译： 本发明一般涉及一种系统和方法，用于经由I / O高速缓存将数据从系统存储器提取到与PCI总线通信的设备。 概括地说，本发明可以被看作是传达某些提取提示的新颖方式; 即指定要从系统内存中提取的数据的某些质量的提示。 在操作中，I / O缓存可以使用这样的提示来更有效地管理通过它的数据。 作为一个例子，如果基于提示，I / O缓存的控制器知道（或假设）所取出的数据是ATM数据，则它也将精确地知道（基于ATM数据的性质）， 将48个字节的数据有效载荷发送到请求设备，并且I / O缓存可以精确地预取这一数量的数据（通常为一个或两个高速缓存行）。 根据本发明的一个方面，这种系统包括插入在系统存储器和PCI总线之间的输入/输出（I / O）高速缓冲存储器，其中高速缓冲存储器具有多个形式的内部存储器空间 高速缓存中的数据线。 该系统还包括用于每个PCI主机的多个寄存器，其被配置为定义提取准则。 最后，该系统包括一个寄存器选择器，被配置为在多个寄存器中选择一个活动寄存器，其中由该寄存器指定该设备的取得标准。