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1.发明授权Methods and systems for locally generating non-integral divided clocks with centralized state machines 失效用集中式状态机本地生成非积分分时钟的方法和系统公开(公告)号：US07368958B2
公开(公告)日：2008-05-06
申请号：US11419224
申请日：2006-05-19
IPC分类号： H03K21/00
摘要： A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the state machine generating a control signal in response to the counter. The control signal is provided to staging latches, the staging latches generating a clock high signal and a clock low signal. Local pass gates generate an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.
摘要翻译： 用于在芯片上本地产生比率时钟的方法包括产生具有全局时钟周期的全局时钟信号。 集中式状态机包括响应于非整数数量的全局时钟周期的整个周期的计数器，状态机响应于计数器产生控制信号。 控制信号被提供给分段锁存器，分段锁存器产生时钟高信号和时钟低电平信号。 响应于全局时钟信号，时钟高电平信号和时钟低电平信号，本地通道门产生（n + 0.5）至1时钟信号。
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2.发明申请Methods and Systems for Locally Generating Non-Integral Divided Clocks with Centralized State Machines 审中-公开用集中式机器本地生成非积分分时钟的方法与系统公开(公告)号：US20080191753A1
公开(公告)日：2008-08-14
申请号：US12106533
申请日：2008-04-21
IPC分类号： H03K21/00
摘要： A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the state machine generating a control signal in response to the counter. The control signal is provided to staging latches, the staging latches generating a clock high signal and a clock low signal. Local pass gates generate an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.
摘要翻译： 用于在芯片上本地产生比率时钟的方法包括产生具有全局时钟周期的全局时钟信号。 集中式状态机包括响应于非整数数量的全局时钟周期的整个周期的计数器，状态机响应于计数器产生控制信号。 控制信号被提供给分段锁存器，分段锁存器产生时钟高信号和时钟低电平信号。 响应于全局时钟信号，时钟高电平信号和时钟低电平信号，本地通道门产生（n + 0.5）至1时钟信号。
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3.发明授权Method for locally generating non-integral divided clocks with centralized state machines 失效用集中式状态机本地生成非积分分时钟的方法公开(公告)号：US07355460B2
公开(公告)日：2008-04-08
申请号：US11341038
申请日：2006-01-27
IPC分类号： G06F1/04
摘要： A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine is provided that includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the centralized state machine generating a control signal in response to the counter. The control signal is provided to staging latches, the staging latches generating a clock high signal and a clock low signal, the clock high and clock low signal having patterns derived from a waveform of a target divided ratio clock and the clock high and clock low signals have patterns that match the targeted divided clock frequency and duty cycle. Local pass gate are provided for generating an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.
摘要翻译： 用于在芯片上本地产生比率时钟的方法包括产生具有全局时钟周期的全局时钟信号。 提供集中式状态机，其包括响应于非整数数量的全局时钟周期的整个周期的计数器，所述集中式状态机响应于所述计数器产生控制信号。 控制信号被提供给分段锁存器，分段锁存器产生时钟高信号和时钟低信号，时钟高电平和时钟低电平信号具有从目标分频比时钟的波形导出的模式，以及时钟高电平和时钟低电平信号 具有匹配目标分频时钟频率和占空比的模式。 本地通路门用于响应于全局时钟信号，时钟高电平信号和时钟低电平信号产生（n + 0.5）至1时钟信号。
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公开(公告)号：US06629280B1
公开(公告)日：2003-09-30
申请号：US09669462
申请日：2000-09-25
IPC分类号： G01B3128
CPC分类号： G11C29/12015 , G11C29/14
摘要： An exemplary embodiment of the invention is a method and apparatus for delaying the start of an array built-in self-test (ABIST) until after the ABIST memory arrays have been started. The length of the delay is determined by the value in a programmable delay located on the integrated circuit. The initiation of the ABIST test is delayed by the time specified in the programmable delay.
摘要翻译： 本发明的示例性实施例是一种用于在ABIST存储器阵列启动之后延迟阵列内置自检（ABIST）的启动的方法和装置。 延迟的长度由位于集成电路上的可编程延迟中的值确定。 ABIST测试的启动延迟了可编程延迟中指定的时间。
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公开(公告)号：US07129764B2
公开(公告)日：2006-10-31
申请号：US11056024
申请日：2005-02-11
IPC分类号： G06F1/04
CPC分类号： G06F1/04
摘要： A system for locally generating a ratio clock from a global clock based on a global clock gate signal includes a staging unit, a pass gate, and a state machine. The state machine is electrically connected to an output of the staging unit and an input of the pass gate. The state machine includes state elements and associated logic. The associated logic is configured to allow said state elements to pass through a number of logic states for every same number of consecutive edges of the global clock when the associated logic is enabled. The number is a positive integer.
摘要翻译： 用于基于全局时钟门信号从全局时钟本地生成比率时钟的系统包括分段单元，通过门和状态机。 状态机电连接到分段单元的输出端和通孔的输入端。 状态机包括状态元素和相关逻辑。 相关联的逻辑被配置为当相关联的逻辑被使能时允许所述状态元件对于全局时钟的每个相同数量的连续边缘通过多个逻辑状态。 数字是一个正整数。
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6.发明授权Circuits for locally generating non-integral divided clocks with centralized state machines 失效用集中式状态机本地生成非积分分时钟的电路公开(公告)号：US07319348B2
公开(公告)日：2008-01-15
申请号：US11341032
申请日：2006-01-27
IPC分类号： G06F1/04
CPC分类号： H03K23/502
摘要： Circuitry for locally generating a ratio clock on a chip. The circuitry includes circuitry for generating a global clock signal having a global clock cycle. A state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles. The state machine generates a control signal in response to the counter. Staging latches receive the control signal and generate a clock high signal and a clock low signal, the clock high signal and the clock low signal having patterns derived from a waveform of a target divided ratio clock, the clock high signal and the clock low signals have patterns that match the targeted divided clock frequency and duty cycle. A local pass gate receives the clock low signal and the clock high signal and generates an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.
摘要翻译： 本地生成芯片上的比率时钟的电路。 该电路包括用于产生具有全局时钟周期的全局时钟信号的电路。 状态机包括响应于非整数个全局时钟周期的整个周期的计数器。 状态机响应于计数器产生控制信号。 分段锁存器接收控制信号并产生时钟高信号和时钟低信号，时钟高信号和时钟低信号具有从目标分频比时钟的波形导出的模式，时钟高信号和时钟低信号具有 符合目标分频时钟频率和占空比的模式。 本地通过门接收时钟低电平信号和时钟高电平信号，并响应于全局时钟信号，时钟高电平信号和时钟低电平信号产生（n + 0.5）至1时钟信号。
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公开(公告)号：US06629281B1
公开(公告)日：2003-09-30
申请号：US09669917
申请日：2000-09-26
IPC分类号： G11C2900
CPC分类号： G11C29/12015 , G01R31/3187 , G11C29/14 , G11C29/44 , G11C2029/1206 , G11C2029/1208
摘要： This invention describes a method and apparatus, contained within an integrated circuit, for isolating failure by precisely controlling the number of clocks applied during built-in self-test (BIST). A programmable clock counter, on the integrated circuit, stores a specified number of clock cycles and sends a signal to stop a BIST engine once the specified number of clock cycles have been generated. The intermediate results can then be mapped bit by bit in order to isolate the cause of failure.
摘要翻译： 本发明描述了一种包含在集成电路内的方法和装置，用于通过精确地控制在内置自检（BIST）期间施加的时钟数来隔离故障。 在集成电路上的可编程时钟计数器存储指定数量的时钟周期，并在生成指定数量的时钟周期后发送一个信号来停止BIST引擎。 然后可以逐个映射中间结果，以隔离故障原因。
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公开(公告)号：US6125465A
公开(公告)日：2000-09-26
申请号：US4873
申请日：1998-01-09
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318552
摘要： A method of LBIST testing of an entire chip (i.e. all logic and arrays are getting system clocks) enables finding intermittent fault in an area, such as the L1 cache. Latches such as GPTR latches can be set such that the L1 cache will no longer receive system clocks during LBIST testing. Logic causing an intermittent failure will no longer receive system clocks and hence will no longer cause intermittent LBIST signatures. LBIST testing can proceed on looking for the next failure, if one existed, or proving that the remaining logic contains no faults. Generally, a chip, has a basic clock distribution and control system that the chip is divided into a number (N) of functional units with each unit receiving system clocks from its own clock control macro. Each clock control macro receives an oscillator signal and a bit from the GPTR (General Purpose Test Register). All the functional units contain latches that are connected into one scan chain.
摘要翻译： 整个芯片（即所有逻辑和阵列正在获得系统时钟）的LBIST测试的方法使得能够在诸如L1高速缓存的区域中发现间歇性故障。 可以设置诸如GPTR锁存器的锁存器，使得L1缓存在LBIST测试期间将不再接收系统时钟。 导致间歇性故障的逻辑将不再接收系统时钟，因此不再会导致间歇性LBIST签名。 LBIST测试可以继续寻找下一个故障，如果存在，或证明剩余的逻辑不包含故障。 通常，芯片具有基本的时钟分配和控制系统，该芯片被分成多个（N个）功能单元，每个单元从其自己的时钟控制宏接收系统时钟。 每个时钟控制宏从GPTR（通用测试寄存器）接收振荡器信号和位。 所有功能单元都包含连接到一个扫描链中的锁存器。
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公开(公告)号：US5420467A
公开(公告)日：1995-05-30
申请号：US830217
申请日：1992-01-31
CPC分类号： H03K5/131
摘要： A pulse shaping circuit of the clock stretcher/chopper type which is sufficiently simplified to be included on an integrated circuit chip with other circuits without significantly reducing the chip area on which such other circuits may be formed achieves a fast recovery time by developing differential delays in response to each of two different characteristics of a signal input to a delay line. Pulse stretching is accomplished by a latch circuit and pulse chopping is accomplished by a delay arrangement which controls the latching action and the output signal. The delay arrangement may also be made programmable. By controlling the latching and the output signal in response to the delay line, a wide range of duty cycles of input and output signals may be accommodated, even at extremely high frequencies. By providing for asymmetric delays, preferably by an asymmetric logic gate monitoring selected stages of a multi-stage delay line, the recovery period of the circuit is made independent of the total delay of the delay line.
摘要翻译： 时钟延迟器/斩波器类型的脉冲整形电路被充分简化以便与其他电路一起包含在集成电路芯片中，而不会显着地减少可以形成这种其他电路的芯片面积，通过开发差分延迟来实现快速恢复时间 响应于输入到延迟线的信号的两个不同特性中的每一个。 脉冲拉伸由锁存电路完成，脉冲斩波通过控制锁存动作和输出信号的延迟装置完成。 延迟布置也可以是可编程的。 通过响应于延迟线控制锁存和输出信号，即使在极高的频率下也可以容纳输入和输出信号的宽范围的占空比。 通过提供不对称延迟，优选地通过非对称逻辑门监视多级延迟线的选定级，电路的恢复周期与延迟线的总延迟无关。
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公开(公告)号：US20110307747A1
公开(公告)日：2011-12-15
申请号：US12797181
申请日：2010-06-09
申请人： Kevin J. Duffy , William V. Huott , Pradip Patel , Daniel Rodko
发明人： Kevin J. Duffy , William V. Huott , Pradip Patel , Daniel Rodko
摘要： An array built-in self test (ABIST) system includes a first latch having a first data input, a first scan input and first output and a second latch having a second data input, a second scan input and a second output. The system also includes a first ABIST logic block coupled to the first output that compares a first expected value with a first data value received at the first data input and provided to the first ABIST logic block after a first clock is applied to the first latch. The system also includes a second ABIST logic block coupled to the second output that compares a second expected value with a second data value received at the second data input and provided to the second ABIST logic block after a second clock is applied to the second latch.
摘要翻译： 阵列内置自检（ABIST）系统包括具有第一数据输入，第一扫描输入和第一输出的第一锁存器以及具有第二数据输入的第二锁存器，第二扫描输入端和第二输出端。 该系统还包括耦合到第一输出的第一ABIST逻辑块，该第一ABIST逻辑块将第一预期值与在第一数据输入端接收的第一数据值进行比较，并在第一时钟施加到第一锁存器之后提供给第一ABIST逻辑块。 该系统还包括耦合到第二输出的第二ABIST逻辑块，该第二ABIST逻辑块将第二预期值与在第二数据输入端接收的第二数据值进行比较，并在第二时钟施加到第二锁存器之后提供给第二ABIST逻辑块。
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