公开(公告)号：US08666105B2

公开(公告)日：2014-03-04

申请号：US12905380

申请日：2010-10-15

申请人： William Walker ,  Chris Matthews

发明人： William Walker ,  Chris Matthews

IPC分类号： H04R25/00

CPC分类号： B60R11/0217 ,  B60R2011/0036 ,  B60R2011/0052 ,  H04R1/026

摘要： Disclosed herein are embodiments of a speaker mounting assembly. In one such embodiment, the speaker mounting assembly comprises a speaker housing having a housing support surface, a speaker mounting bracket having a base surface, a projection extending from one of the speaker housing and the speaker mounting bracket and a mounting structure formed on the other of the speaker housing and the speaker mounting bracket. The mounting structure is configured to receive the projection such that the housing support surface contacts the base surface when the projection is received in the mounting structure. The mounting structure has an anti-rotation structure configured to prevent rotation of the speaker housing with respect to the speaker mounting bracket.

摘要翻译： 这里公开了扬声器安装组件的实施例。 在一个这样的实施例中，扬声器安装组件包括具有壳体支撑表面的扬声器壳体，具有基座表面的扬声器安装支架，从扬声器壳体和扬声器安装支架中的一个延伸的突出部和在另一个上形成的安装结构 的扬声器外壳和扬声器安装支架。 安装结构构造成接收突起，使得当突起被接收在安装结构中时，壳体支撑表面接触基座表面。 安装结构具有防旋转结构，其构造成防止扬声器壳体相对于扬声器安装支架旋转。

公开(公告)号：US20120091866A1

公开(公告)日：2012-04-19

申请号：US12905380

申请日：2010-10-15

申请人： William Walker ,  Chris Matthews

发明人： William Walker ,  Chris Matthews

IPC分类号： A47B81/06

CPC分类号： B60R11/0217 ,  B60R2011/0036 ,  B60R2011/0052 ,  H04R1/026

摘要： Disclosed herein are embodiments of a speaker mounting assembly. In one such embodiment, the speaker mounting assembly comprises a speaker housing having a housing support surface, a speaker mounting bracket having a base surface, a projection extending from one of the speaker housing and the speaker mounting bracket and a mounting structure formed on the other of the speaker housing and the speaker mounting bracket. The mounting structure is configured to receive the projection such that the housing support surface contacts the base surface when the projection is received in the mounting structure. The mounting structure has an anti-rotation structure configured to prevent rotation of the speaker housing with respect to the speaker mounting bracket.

摘要翻译： 这里公开了扬声器安装组件的实施例。 在一个这样的实施例中，扬声器安装组件包括具有壳体支撑表面的扬声器壳体，具有基座表面的扬声器安装支架，从扬声器壳体和扬声器安装支架中的一个延伸的突出部和在另一个上形成的安装结构 的扬声器外壳和扬声器安装支架。 安装结构构造成接收突起，使得当突起被接收在安装结构中时，壳体支撑表面接触基座表面。 安装结构具有防旋转结构，其构造成防止扬声器壳体相对于扬声器安装支架旋转。

公开(公告)号：US20070041405A1

公开(公告)日：2007-02-22

申请号：US11166030

申请日：2005-06-23

申请人： Muraleedhara Navada ,  Tim Frodsham ,  Sanjay Dabral ,  Allen Baum ,  Chris Matthews ,  Chris Gianos ,  Rahul Shah ,  Theodore Schoenborn

发明人： Muraleedhara Navada ,  Tim Frodsham ,  Sanjay Dabral ,  Allen Baum ,  Chris Matthews ,  Chris Gianos ,  Rahul Shah ,  Theodore Schoenborn

IPC分类号： H04J3/06

CPC分类号： H04L7/10 ,  H04L7/0008 ,  H04L7/0041

摘要： A discussion of improving integrated device deterministic response to test vectors. For example, limiting the transmission delay for an integrated device's response within known bounds by synchronizing an initialization training sequence to a reset deassertion. Specifically, the proposal facilitates response determinism from the DUT by synchronizing training sequences and subsequently synchronizing flit transmission to reset assertion as sampled by reference clock.

摘要翻译： 关于改进对测试矢量的集成设备确定性响应的讨论。 例如，通过将初始化训练序列同步到复位失效来限制在已知边界内的集成设备的响应的传输延迟。 具体地，该提议通过使训练序列同步并随后将颤振传输同步到由参考时钟采样的复位断言来促进来自DUT的响应确定性。

公开(公告)号：US20080162766A1

公开(公告)日：2008-07-03

申请号：US11618509

申请日：2006-12-29

申请人： Blaise Fanning ,  Chris Matthews ,  Chunyu Zhang

发明人： Blaise Fanning ,  Chris Matthews ,  Chunyu Zhang

IPC分类号： G06F13/14

CPC分类号： G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

摘要： Techniques involving the transfer of signals across interconnection media are disclosed. For instance, an apparatus may include a configuration module and a driver module. The configuration module establishes an operational mode setting from a first operational mode and a second operational mode. The driver module may operate according to this setting. For instance, according to the first operational mode, the driver module continually drives an interconnection medium. However, for the second operational mode, the driver module drives the interconnection medium when it receives an input signal and otherwise refrains from driving the interconnection medium. According to the first operational mode, a termination module may couple a pull-up resistance to the interconnection medium. However, for the second operational mode, the termination module does not couple such a resistance to the interconnection medium.

摘要翻译： 公开了涉及通过互连介质传送信号的技术。 例如，设备可以包括配置模块和驱动器模块。 配置模块从第一操作模式和第二操作模式建立操作模式设置。 驱动器模块可以根据此设置进行操作。 例如，根据第一操作模式，驱动器模块连续驱动互连介质。 然而，对于第二操作模式，当接收到输入信号并且禁止驱动互连介质时，驱动器模块驱动互连介质。 根据第一操作模式，终端模块可以将上拉电阻耦合到互连介质。 然而，对于第二操作模式，终端模块不将这种电阻耦合到互连介质。

公开(公告)号：US20070157048A1

公开(公告)日：2007-07-05

申请号：US11322681

申请日：2005-12-30

申请人： Alexander Levin ,  Sriram Badrinarayanan ,  Chris Matthews

发明人： Alexander Levin ,  Sriram Badrinarayanan ,  Chris Matthews

IPC分类号： G06F1/12 ,  G06F13/42

CPC分类号： G06F13/4077

摘要： A method and apparatus is described herein for serializing input data streams into an output data stream. A first and second input data stream are sampled upon rising edges of a first and second clocking signal, respectively, to reduce jitter from dependence on the falling edges of the clocking signals. The second clocking signal is 180 degrees out of phase with the first clocking signal to sample the first input data stream in the first unit interval of an output data stream and the second input data stream in the second unit interval of the output data stream. Consequently, a serialized output data stream is driven at twice the frequency of both the first and the second input data streams, including logical information from the first and second input data streams every period of the output data stream.

摘要翻译： 本文描述了将输入数据流串行化为输出数据流的方法和装置。 分别在第一和第二时钟信号的上升沿对第一和第二输入数据流进行采样，以便根据时钟信号的下降沿降低抖动。 第二时钟信号与第一时钟信号相差180度，以在输出数据流的第一单位间隔中采样第一输入数据流，并在输出数据流的第二单位间隔采样第二输入数据流。 因此，序列化的输出数据流以第一和第二输入数据流的频率的两倍被驱动，包括来自输出数据流每个周期的第一和第二输入数据流的逻辑信息。