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    SIGNAL TECHNIQUES FOR BUS INTERFACES
    1.
    发明申请
    SIGNAL TECHNIQUES FOR BUS INTERFACES 审中-公开
    总线接口信号技术

    公开(公告)号：US20080162766A1

    公开(公告)日：2008-07-03

    申请号：US11618509

    申请日：2006-12-29

    申请人： Blaise Fanning ,  Chris Matthews ,  Chunyu Zhang

    发明人： Blaise Fanning ,  Chris Matthews ,  Chunyu Zhang

    IPC分类号： G06F13/14

    CPC分类号： G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

    摘要： Techniques involving the transfer of signals across interconnection media are disclosed. For instance, an apparatus may include a configuration module and a driver module. The configuration module establishes an operational mode setting from a first operational mode and a second operational mode. The driver module may operate according to this setting. For instance, according to the first operational mode, the driver module continually drives an interconnection medium. However, for the second operational mode, the driver module drives the interconnection medium when it receives an input signal and otherwise refrains from driving the interconnection medium. According to the first operational mode, a termination module may couple a pull-up resistance to the interconnection medium. However, for the second operational mode, the termination module does not couple such a resistance to the interconnection medium.

    摘要翻译： 公开了涉及通过互连介质传送信号的技术。 例如，设备可以包括配置模块和驱动器模块。 配置模块从第一操作模式和第二操作模式建立操作模式设置。 驱动器模块可以根据此设置进行操作。 例如，根据第一操作模式，驱动器模块连续驱动互连介质。 然而，对于第二操作模式，当接收到输入信号并且禁止驱动互连介质时，驱动器模块驱动互连介质。 根据第一操作模式，终端模块可以将上拉电阻耦合到互连介质。 然而，对于第二操作模式，终端模块不将这种电阻耦合到互连介质。

    Remapping memory devices during operation
    9.
    发明授权
    Remapping memory devices during operation 有权
    操作期间重映射存储器件

    公开(公告)号：US06816986B1

    公开(公告)日：2004-11-09

    申请号：US09473483

    申请日：1999-12-28

    申请人： Blaise Fanning

    发明人： Blaise Fanning

    IPC分类号： H02H305

    CPC分类号： G06F11/1666 ,  G06F11/1658 ,  G06F11/20 ,  G11C29/76

    摘要： According to the invention, systems, apparatus and methods are disclosed for automatically replacing semiconductor based memory in a system while that system is operating. Replacement is accomplished by blocking access to the memory devices to be swapped, copying the contents of the faulty device to the replacement device, swapping the IDs of the two devices, and re-enabling access to the replaced device. This replacement is triggered by interrupts from the error detection logic. After replacement, the system automatically checks the faulty device to determine its suitability for use as a spare in the future. The determination is made by repeatedly writing and reading a pseudo-random pattern into the device and logging any errors.

    摘要翻译： 根据本发明，公开了系统，装置和方法，用于在系统运行时自动替换系统中的半导体存储器。 替换是通过阻止访问要交换的存储设备，将故障设备的内容复制到替换设备，交换两个设备的ID，以及重新启用对更换的设备的访问来实现的。 该更换由错误检测逻辑的中断触发。 更换后，系统会自动检查故障设备，以确定其将来适合作为备用设备使用。 通过重复写入和读取伪随机模式到设备中并记录任何错误来进行确定。

    Translation of virtual addresses in a computer graphics system
    10.
    发明授权
    Translation of virtual addresses in a computer graphics system 失效
    在计算机图形系统中翻译虚拟地址

    公开(公告)号：US5313577A

    公开(公告)日：1994-05-17

    申请号：US748357

    申请日：1991-08-21

    申请人： Kim Meinerth ,  Colyn Case ,  Chris Franklin ,  Blaise Fanning ,  Rodney Gamache

    发明人： Kim Meinerth ,  Colyn Case ,  Chris Franklin ,  Blaise Fanning ,  Rodney Gamache

    IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F12/10 ,  G09G5/06 ,  G09G5/08 ,  G09G5/39 ,  G06F15/00

    CPC分类号： G09G5/39 ,  G06F12/1027 ,  G06F9/3879 ,  G09G5/06 ,  G09G5/08 ,  G06F12/0831 ,  G09G2360/121 ,  G09G2360/127

    摘要： A computer graphics processor capable of reading from, and writing to, virtual memory. The invention provides a graphics processing unit which includes, among other things, an graphic processor in the form of an address generator which retrieves data from memory locations, and writes data to memory locations. The address generator retrieves data from memory locations memory access request directly to a memory control unit, which retrieves the contents of the memory location. Prior to issuing the request, the address generator sends the address to a virtual translation unit, which translates the virtual address to a physical address. The virtual translation/FIFO control unit also contains three translation buffers, in which are stored the most recently accessed virtual addresses, which, in many situations, enables the virtual translation/FIFO control unit to translate the virtual address using less memory accesses.

    摘要翻译： 能够读取和写入虚拟内存的计算机图形处理器。 本发明提供了一种图形处理单元，其中包括地址发生器形式的图形处理器，其从存储器位置检索数据，并将数据写入存储单元。 地址生成器将存储器存储器访问请求中的数据直接检索到存储器控制单元，存储器控制单元检索存储器位置的内容。 在发出请求之前，地址生成器将地址发送到虚拟转换单元，该虚拟转换单元将虚拟地址转换为物理地址。 虚拟转换/ FIFO控制单元还包含三个转换缓冲器，其中存储最近访问的虚拟地址，在许多情况下，虚拟转换/ FIFO控制单元能够使用较少的存储器访问来转换虚拟地址。