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公开(公告)号：US11316106B2
公开(公告)日：2022-04-26
申请号：US17109147
申请日：2020-12-02
Applicant: Winbond Electronics Corp.
Inventor： Chung-Hsuan Wang , Yu-Ting Chen , Tz-Hau Guo , Chang-Hsuan Wu , Chiung-Lin Hsu
Abstract: Provided are a resistive random access memory and a manufacturing method thereof. The resistive random access memory includes first, second, and third electrodes, a variable resistance layer, a selection layer, and first and second bit lines. The second electrode and the third electrode are on the first electrode. The second and third electrodes are separated from each other and overlapped with the sidewall and the top surface of the first electrode. The variable resistance layer is between the first and second electrodes and between the first and third electrodes. The selection layer is between the variable resistance layer and the first electrode. The first bit line is on the second electrode and electrically connected to the second electrode via a first contact. The second bit line is on the third electrode and electrically connected to the third electrode via a second contact.
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公开(公告)号：US20210193918A1
公开(公告)日：2021-06-24
申请号：US17109147
申请日：2020-12-02
Applicant: Winbond Electronics Corp.
Inventor： Chung-Hsuan Wang , Yu-Ting Chen , Tz-Hau Guo , Chang-Hsuan Wu , Chiung-Lin Hsu
Abstract: Provided are a resistive random access memory and a manufacturing method thereof. The resistive random access memory includes first, second, and third electrodes, a variable resistance layer, a selection layer, and first and second bit lines. The second electrode and the third electrode are on the first electrode. The second and third electrodes are separated from each other and overlapped with the sidewall and the top surface of the first electrode. The variable resistance layer is between the first and second electrodes and between the first and third electrodes. The selection layer is between the variable resistance layer and the first electrode. The first bit line is on the second electrode and electrically connected to the second electrode via a first contact.
The second bit line is on the third electrode and electrically connected to the third electrode via a second contact.-
公开(公告)号：US10950302B1
公开(公告)日：2021-03-16
申请号：US16877511
申请日：2020-05-19
Applicant: Winbond Electronics Corp.
Inventor： Chang-Hsuan Wu
Abstract: A resistive memory device including a substrate, an isolation structure, a word line, a source line, a bit line and a resistive memory is provided. The substrate includes a body region, and first, second and third doped regions, the first and second doped regions are spaced apart from each other by the body region. The isolation structure is disposed in the substrate, and the second doped region and the third doped region are spaced apart from each other by the isolation structure. The word line is disposed on the substrate, the first and second doped regions are located at opposite sides of the word line, and the first and third doped regions are located at the opposite sides of the word line. The source line is disposed on the substrate and electrically connected with the first doped region. The bit line and the resistive memory are disposed on the substrate, and the third doped region is electrically connected with the bit line via the resistive memory.
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