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公开(公告)号：US11316106B2
公开(公告)日：2022-04-26
申请号：US17109147
申请日：2020-12-02
发明人： Chung-Hsuan Wang , Yu-Ting Chen , Tz-Hau Guo , Chang-Hsuan Wu , Chiung-Lin Hsu
摘要： Provided are a resistive random access memory and a manufacturing method thereof. The resistive random access memory includes first, second, and third electrodes, a variable resistance layer, a selection layer, and first and second bit lines. The second electrode and the third electrode are on the first electrode. The second and third electrodes are separated from each other and overlapped with the sidewall and the top surface of the first electrode. The variable resistance layer is between the first and second electrodes and between the first and third electrodes. The selection layer is between the variable resistance layer and the first electrode. The first bit line is on the second electrode and electrically connected to the second electrode via a first contact. The second bit line is on the third electrode and electrically connected to the third electrode via a second contact.
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公开(公告)号：US11176996B2
公开(公告)日：2021-11-16
申请号：US15930469
申请日：2020-05-13
发明人： Ping-Kun Wang , Ming-Che Lin , Yu-Ting Chen , Chang-Tsung Pai , Shao-Ching Liao , Chi-Ching Liu
摘要： Provided is a resistive random access memory (RRAM) including at least one memory cell. The at least one memory cell includes a top electrode, a bottom electrode, a data storage layer, an oxygen gettering layer, a first barrier layer, and an oxygen supplying layer. The data storage layer is disposed between the top electrode and the bottom electrode. The oxygen gettering layer is disposed between the data storage layer and the top electrode. The first barrier layer is disposed between the oxygen gettering layer and the data storage layer. The oxygen supplying layer is disposed between the oxygen gettering layer and the top electrode and/or between the oxygen gettering layer and the first barrier layer.
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公开(公告)号：US11011231B2
公开(公告)日：2021-05-18
申请号：US16849976
申请日：2020-04-15
发明人： Ping-Kun Wang , Chang-Tsung Pai , Yu-Ting Chen , He-Hsuan Chao , Ming-Che Lin , Frederick Chen
摘要： A data write-in method and a non-volatile memory are provided. The data write-in method includes: providing a reset voltage to a plurality of selected memory cells according to a first flag, and recursively performing a reset process for the plurality of selected memory cells; setting a second flag according to a plurality of first verification currents of the plurality of selected memory cells; and under a condition that the second flag is set: providing a set voltage to the plurality of selected memory cells according to a resistance of the plurality of selected memory cells; and setting the first flag according to a plurality of second verification currents of the plurality of selected memory cells.
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公开(公告)号：US20210074356A1
公开(公告)日：2021-03-11
申请号：US16849976
申请日：2020-04-15
发明人： Ping-Kun Wang , Chang-Tsung Pai , Yu-Ting Chen , He-Hsuan Chao , Ming-Che Lin , Frederick Chen
IPC分类号： G11C13/00
摘要： A data write-in method and a non-volatile memory are provided. The data write-in method includes: providing a reset voltage to a plurality of selected memory cells according to a first flag, and recursively performing a reset process for the plurality of selected memory cells; setting a second flag according to a plurality of first verification currents of the plurality of selected memory cells; and under a condition that the second flag is set: providing a set voltage to the plurality of selected memory cells according to a resistance of the plurality of selected memory cells; and setting the first flag according to a plurality of second verification currents of the plurality of selected memory cells.
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公开(公告)号：US20220068382A1
公开(公告)日：2022-03-03
申请号：US17458559
申请日：2021-08-27
发明人： Ming-Che Lin , Min-Chih Wei , Ping-Kun Wang , Yu-Ting Chen , Chih-Cheng Fu , Chang-Tsung Pai
IPC分类号： G11C13/00
摘要： A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.
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公开(公告)号：US20220028454A1
公开(公告)日：2022-01-27
申请号：US17495778
申请日：2021-10-06
发明人： Ping-Kun Wang , Ming-Che Lin , Yu-Ting Chen , Chang-Tsung Pai , Shao-Ching Liao , Chi-Ching Liu
摘要： Provided is a resetting method of a resistive random access memory (RRAM) including the following steps. A first resetting operation and a first verifying operation on the at least one resistive memory cell are performed. Whether to perform a second resetting operation according to a verifying result of the first verifying operation is determined. A second verifying operation is performed after the second resetting operation is determined to be performed and is finished. To determine whether to perform a healing resetting operation according to a verifying result of the second verifying operation, which comprises: performing the healing resetting operation when a verifying current of the second verifying operation is greater than a predetermined current, wherein a resetting voltage of the healing resetting operation is greater than a resetting voltage of the second resetting operation.
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公开(公告)号：US20210193918A1
公开(公告)日：2021-06-24
申请号：US17109147
申请日：2020-12-02
发明人： Chung-Hsuan Wang , Yu-Ting Chen , Tz-Hau Guo , Chang-Hsuan Wu , Chiung-Lin Hsu
摘要： Provided are a resistive random access memory and a manufacturing method thereof. The resistive random access memory includes first, second, and third electrodes, a variable resistance layer, a selection layer, and first and second bit lines. The second electrode and the third electrode are on the first electrode. The second and third electrodes are separated from each other and overlapped with the sidewall and the top surface of the first electrode. The variable resistance layer is between the first and second electrodes and between the first and third electrodes. The selection layer is between the variable resistance layer and the first electrode. The first bit line is on the second electrode and electrically connected to the second electrode via a first contact.
The second bit line is on the third electrode and electrically connected to the third electrode via a second contact.-
公开(公告)号：US20210057640A1
公开(公告)日：2021-02-25
申请号：US16991055
申请日：2020-08-12
发明人： Wen-Chia Ou , Chih-Chao Huang , Min-Chih Wei , Yu-Ting Chen , Chi-Ching Liu
摘要： A method of fabricating a semiconductor device includes the following steps. A plurality of doped regions are formed in a substrate. A first dielectric layer is formed on the substrate. A plurality of first contacts and second contacts are formed in the first dielectric layer to be connected to the plurality of doped regions. A memory element is formed on the first dielectric layer. The memory element is electrically connected to the second contact. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer surrounds the memory element. A conductive line is formed in the second dielectric layer. A top surface of the conductive line is at a same level as a top surface of the memory element, and the conductive line is electrically connected to the plurality of first contacts.
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公开(公告)号：US20210012839A1
公开(公告)日：2021-01-14
申请号：US15930469
申请日：2020-05-13
发明人： Ping-Kun Wang , Ming-Che Lin , Yu-Ting Chen , Chang-Tsung Pai , Shao-Ching Liao , Chi-Ching Liu
摘要： Provided is a resistive random access memory (RRAM) including at least one memory cell. The at least one memory cell includes a top electrode, a bottom electrode, a data storage layer, an oxygen gettering layer, a first barrier layer, and an oxygen supplying layer. The data storage layer is disposed between the top electrode and the bottom electrode. The oxygen gettering layer is disposed between the data storage layer and the top electrode. The first barrier layer is disposed between the oxygen gettering layer and the data storage layer. The oxygen supplying layer is disposed between the oxygen gettering layer and the top electrode and/or between the oxygen gettering layer and the first barrier layer.
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公开(公告)号：US11908516B2
公开(公告)日：2024-02-20
申请号：US17458559
申请日：2021-08-27
发明人： Ming-Che Lin , Min-Chih Wei , Ping-Kun Wang , Yu-Ting Chen , Chih-Cheng Fu , Chang-Tsung Pai
CPC分类号： G11C13/0038 , G11C13/004 , G11C13/0026 , G11C13/0028 , G11C2213/79
摘要： A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.
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