公开(公告)号：US11316106B2

公开(公告)日：2022-04-26

申请号：US17109147

申请日：2020-12-02

Applicant: Winbond Electronics Corp.

Inventor： Chung-Hsuan Wang ,  Yu-Ting Chen ,  Tz-Hau Guo ,  Chang-Hsuan Wu ,  Chiung-Lin Hsu

IPC: H01L45/00 ,  H01L27/24

Abstract: Provided are a resistive random access memory and a manufacturing method thereof. The resistive random access memory includes first, second, and third electrodes, a variable resistance layer, a selection layer, and first and second bit lines. The second electrode and the third electrode are on the first electrode. The second and third electrodes are separated from each other and overlapped with the sidewall and the top surface of the first electrode. The variable resistance layer is between the first and second electrodes and between the first and third electrodes. The selection layer is between the variable resistance layer and the first electrode. The first bit line is on the second electrode and electrically connected to the second electrode via a first contact. The second bit line is on the third electrode and electrically connected to the third electrode via a second contact.

公开(公告)号：US20230369145A1

公开(公告)日：2023-11-16

申请号：US17741412

申请日：2022-05-10

Applicant: Winbond Electronics Corp.

Inventor： Ming-Chih Hsu ,  Chiung-Lin Hsu

IPC: H01L21/66 ,  H01L23/00 ,  H01L27/108

CPC classification number: H01L22/34 ,  H01L23/562 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888

Abstract: A semiconductor structure includes a substrate, a first support layer, and multiple support pillars. The substrate includes a monitoring region. The monitoring region includes a first region and a second region. The first support layer is located in the first region and the second region, and is located above the substrate. The support pillars are located in the second region. The support pillars penetrate the first support layer and are not connected to each other. Each of the support pillars extends toward the substrate.

公开(公告)号：US20210193918A1

公开(公告)日：2021-06-24

申请号：US17109147

申请日：2020-12-02

Applicant: Winbond Electronics Corp.

Inventor： Chung-Hsuan Wang ,  Yu-Ting Chen ,  Tz-Hau Guo ,  Chang-Hsuan Wu ,  Chiung-Lin Hsu

IPC: H01L45/00 ,  H01L27/24

Abstract: Provided are a resistive random access memory and a manufacturing method thereof. The resistive random access memory includes first, second, and third electrodes, a variable resistance layer, a selection layer, and first and second bit lines. The second electrode and the third electrode are on the first electrode. The second and third electrodes are separated from each other and overlapped with the sidewall and the top surface of the first electrode. The variable resistance layer is between the first and second electrodes and between the first and third electrodes. The selection layer is between the variable resistance layer and the first electrode. The first bit line is on the second electrode and electrically connected to the second electrode via a first contact.
The second bit line is on the third electrode and electrically connected to the third electrode via a second contact.

公开(公告)号：US11758740B2

公开(公告)日：2023-09-12

申请号：US17224152

申请日：2021-04-07

Applicant: Winbond Electronics Corp.

Inventor： Chang-Tsung Pai ,  Chiung-Lin Hsu ,  Yu-Ting Chen ,  Ming-Che Lin ,  Chi-Ching Liu

IPC: H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/30 ,  H10N70/011 ,  H10N70/253 ,  H10N70/8265 ,  H10N70/841

Abstract: A three-dimensional semiconductor device includes multiple semiconductor device layers on a substrate, wherein each layer includes a first stacked structure, a first gate dielectric layer, a first semiconductor layer, a first channel layer, a first source region, a first drain region, and a first resistive random access memory cell. The first stacked structure on the substrate includes a first insulating layer and a first gate conductor layer. The first gate dielectric layer surrounds a sidewall of the first stacked structure. The first semiconductor layer surrounds a sidewall of the first gate dielectric layer. The first channel layer is in the first semiconductor layer. The first source region and the first drain region are on both sides of the first channel layer in the first semiconductor layer. The first resistive random access memory cell is on a first sidewall of the first semiconductor layer and connected to the first drain region.

公开(公告)号：US20210366986A1

公开(公告)日：2021-11-25

申请号：US17224152

申请日：2021-04-07

Applicant: Winbond Electronics Corp.

Inventor： Chang-Tsung Pai ,  Chiung-Lin Hsu ,  Yu-Ting Chen ,  Ming-Che Lin ,  Chi-Ching Liu

IPC: H01L27/24 ,  H01L45/00

Abstract: A three-dimensional semiconductor device includes multiple semiconductor device layers on a substrate, wherein each layer includes a first stacked structure, a first gate dielectric layer, a first semiconductor layer, a first channel layer, a first source region, a first drain region, and a first resistive random access memory cell. The first stacked structure on the substrate includes a first insulating layer and a first gate conductor layer. The first gate dielectric layer surrounds a sidewall of the first stacked structure. The first semiconductor layer surrounds a sidewall of the first gate dielectric layer. The first channel layer is in the first semiconductor layer. The first source region and the first drain region are on both sides of the first channel layer in the first semiconductor layer. The first resistive random access memory cell is on a first sidewall of the first semiconductor layer and connected to the first drain region.

公开(公告)号：US12142539B2

公开(公告)日：2024-11-12

申请号：US17741412

申请日：2022-05-10

Applicant: Winbond Electronics Corp.

Inventor： Ming-Chih Hsu ,  Chiung-Lin Hsu

IPC: H01L23/00 ,  H01L21/66 ,  H10B12/00

Abstract: A semiconductor structure includes a substrate, a first support layer, and multiple support pillars. The substrate includes a monitoring region. The monitoring region includes a first region and a second region. The first support layer is located in the first region and the second region, and is located above the substrate. The support pillars are located in the second region. The support pillars penetrate the first support layer and are not connected to each other. Each of the support pillars extends toward the substrate.