公开(公告)号：US12106964B2

公开(公告)日：2024-10-01

申请号：US17326334

申请日：2021-05-21

Applicant: Winbond Electronics Corp.

Inventor： Chu-Chun Hsieh ,  Ting-Wei Wu ,  Chih-Jung Ni

IPC: H01L21/033

CPC classification number: H01L21/0338 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337

Abstract: Provided is a patterning method including following steps. A doped polysilicon layer, a core layer, and an undoped polysilicon layer are sequentially formed on a target layer. The undoped polysilicon layer is patterned to form a polysilicon pattern. A first etching process is performed by using the polysilicon pattern as a mask to remove a portion of the core layer to form a core pattern. A second etching process is performed to remove the polysilicon pattern. An atomic layer deposition (ALD) process is performed to form a spacer material on the core pattern and the doped polysilicon layer. A portion of the spacer material is removed to form a spacer on a sidewall of the core pattern. A portion of the core pattern and an underlying doped polysilicon are removed.

公开(公告)号：US11335568B2

公开(公告)日：2022-05-17

申请号：US16872760

申请日：2020-05-12

Applicant: Winbond Electronics Corp.

Inventor： Ting-Wei Wu ,  Cheng-Ta Yang ,  Hsin-Hung Chou

IPC: H01L21/3213 ,  H01L21/311 ,  H01L21/033

Abstract: A method for forming a semiconductor structure is provided. The method includes: forming first and second hard mask layers and a target layer on a substrate; patterning the second hard mask layer to form patterned second hard masks including a second wide mask and second narrow masks; and forming spacers on sidewalls of the second wide mask and the second narrow masks. Then, a photoresist layer is formed to cover the second wide mask and the spacers on the sidewalls of the second wide mask. The second narrow masks and the photoresist layer are removed. And, the first hard mask layer is etched with the spacers and the second wide mask together as a mask to form patterned first hard masks on the target layer, wherein the spacers define a first line width, and the second wide mask and the pair of spacers define a second line width.

公开(公告)号：US20210391174A1

公开(公告)日：2021-12-16

申请号：US17326334

申请日：2021-05-21

Applicant: Winbond Electronics Corp.

Inventor： Chu-Chun Hsieh ,  Ting-Wei Wu ,  Chih-Jung Ni

IPC: H01L21/033

Abstract: Provided is a patterning method including following steps. A doped polysilicon layer, a core layer, and an undoped polysilicon layer are sequentially formed on a target layer. The undoped polysilicon layer are patterned to form a polysilicon pattern. A first etching process is performed by using the polysilicon pattern as a mask to remove a portion of the core layer to form a core pattern. A second etching process is performed to remove the polysilicon pattern. An atomic layer deposition (ALD) process is performed to form a spacer material on the core pattern and the doped polysilicon layer. A portion of the spacer material is removed to form a spacer on a sidewall of the core pattern. A portion of the core pattern and an underlying doped polysilicon are removed.