公开(公告)号：US20210391174A1

公开(公告)日：2021-12-16

申请号：US17326334

申请日：2021-05-21

Applicant: Winbond Electronics Corp.

Inventor： Chu-Chun Hsieh ,  Ting-Wei Wu ,  Chih-Jung Ni

IPC: H01L21/033

Abstract: Provided is a patterning method including following steps. A doped polysilicon layer, a core layer, and an undoped polysilicon layer are sequentially formed on a target layer. The undoped polysilicon layer are patterned to form a polysilicon pattern. A first etching process is performed by using the polysilicon pattern as a mask to remove a portion of the core layer to form a core pattern. A second etching process is performed to remove the polysilicon pattern. An atomic layer deposition (ALD) process is performed to form a spacer material on the core pattern and the doped polysilicon layer. A portion of the spacer material is removed to form a spacer on a sidewall of the core pattern. A portion of the core pattern and an underlying doped polysilicon are removed.

公开(公告)号：US12087619B2

公开(公告)日：2024-09-10

申请号：US18087802

申请日：2022-12-22

Applicant: Winbond Electronics Corp.

Inventor： Chi-Ching Liu ,  Yu-Ting Chen ,  Chang-Tsung Pai ,  Shun-Li Lan ,  Yen-De Lee ,  Chih-Jung Ni

IPC: H01L21/768 ,  H10B99/00

CPC classification number: H01L21/76816 ,  H10B99/00

Abstract: A method for manufacturing a semiconductor device, including the following steps. A plurality of first vias are formed in a first dielectric layer in a memory cell region and a peripheral region. A surface treatment is performed on the plurality of first vias to form a plurality of sacrificial layers. The plurality of sacrificial layers are removed to form a plurality of recesses. A plurality of protective layers are formed in the plurality of recesses. A memory device is formed on the first dielectric layer in the memory cell region. A second dielectric layer is formed on the memory device and on the first dielectric layer. A plurality of second vias is formed in the second dielectric layer in the memory cell region and the peripheral region to electrically connect the memory device in the memory cell region and the first vias in the peripheral region, respectively.

公开(公告)号：US11302705B2

公开(公告)日：2022-04-12

申请号：US16555736

申请日：2019-08-29

Applicant: Winbond Electronics Corp.

Inventor： Chih-Jung Ni ,  Chuan-Chi Chou ,  Yao-Ting Tsai

IPC: H01L27/11521 ,  H01L27/11526 ,  G11C5/06

Abstract: The present invention includes a semiconductor structure having a substrate, a gate structure, and a first spacer. The gate structure includes a floating gate structure, an inter-gate dielectric layer, and a control gate structure. The floating gate structure is disposed on the substrate. The inter-gate dielectric layer is disposed on the floating gate structure. The control gate structure is deposited on the inter-gate dielectric layer and includes an electrode layer, a contact layer and a cap layer. The electrode layer is disposed on the inter-gate dielectric layer. The contact layer is disposed on the electrode layer. The cap layer is disposed on the contact layer. The first spacer is disposed on sidewalls of the control gate structure and covers the electrode layer, the contact layer, and the cap layer. Furthermore, the bottom surface of the first spacer is disposed between the bottom surface and the top surface of the electrode layer.

公开(公告)号：US11839075B2

公开(公告)日：2023-12-05

申请号：US17685786

申请日：2022-03-03

Applicant: Winbond Electronics Corp.

Inventor： Chih-Jung Ni ,  Chuan-Chi Chou ,  Yao-Ting Tsai

IPC: H10B41/30 ,  G11C5/06 ,  H10B41/40

CPC classification number: H10B41/30 ,  G11C5/063 ,  H10B41/40

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a gate structure, and a first spacer. The gate structure includes a floating gate structure disposed on the substrate, an inter-gate dielectric layer disposed on the floating gate structure, and a control gate structure disposed on the inter-gate dielectric layer. The control gate structure includes an electrode layer disposed on the inter-gate dielectric layer, a contact layer disposed on the electrode layer, and a cap layer disposed on the contact layer. The first spacer is disposed on a sidewall of the control gate structure and covering the electrode, the contact layer and the cap layer. A bottom surface of the first spacer is positioned between a bottom surface and a top surface of the electrode layer.

公开(公告)号：US20230129196A1

公开(公告)日：2023-04-27

申请号：US18087802

申请日：2022-12-22

Applicant: Winbond Electronics Corp.

Inventor： Chi-Ching Liu ,  Yu-Ting Chen ,  Chang-Tsung Pai ,  Shun-Li Lan ,  Yen-De Lee ,  Chih-Jung Ni

IPC: H01L21/768 ,  H10B99/00

Abstract: A method for manufacturing a semiconductor device, including the following steps. A plurality of first vias are formed in a first dielectric layer in a memory cell region and a peripheral region. A surface treatment is performed on the plurality of first vias to form a plurality of sacrificial layers. The plurality of sacrificial layers are removed to form a plurality of recesses. A plurality of protective layers are formed in the plurality of recesses. A memory device is formed on the first dielectric layer in the memory cell region. A second dielectric layer is formed on the memory device and on the first dielectric layer. A plurality of second vias is formed in the second dielectric layer in the memory cell region and the peripheral region to electrically connect the memory device in the memory cell region and the first vias in the peripheral region, respectively.

公开(公告)号：US20210287934A1

公开(公告)日：2021-09-16

申请号：US16817572

申请日：2020-03-12

Applicant: Winbond Electronics Corp.

Inventor： Chi-Ching Liu ,  Yu-Ting Chen ,  Chang-Tsung Pai ,  Shun-Li Lan ,  Yen-De Lee ,  Chih-Jung Ni

IPC: H01L21/768 ,  H01L21/8239

Abstract: A method for manufacturing a semiconductor device, including the following steps. A plurality of first vias are formed in a first dielectric layer in a memory cell region and a peripheral region. A surface treatment is performed on the plurality of first vias to form a plurality of sacrificial layers. The plurality of sacrificial layers are removed to form a plurality of recesses. A plurality of protective layers are formed in the plurality of recesses. A memory device is formed on the first dielectric layer in the memory cell region. A second dielectric layer is formed on the memory device and on the first dielectric layer. A plurality of second vias is formed in the second dielectric layer in the memory cell region and the peripheral region to electrically connect the memory device in the memory cell region and the first vias in the peripheral region, respectively.

公开(公告)号：US12106964B2

公开(公告)日：2024-10-01

申请号：US17326334

申请日：2021-05-21

Applicant: Winbond Electronics Corp.

Inventor： Chu-Chun Hsieh ,  Ting-Wei Wu ,  Chih-Jung Ni

IPC: H01L21/033

CPC classification number: H01L21/0338 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337

Abstract: Provided is a patterning method including following steps. A doped polysilicon layer, a core layer, and an undoped polysilicon layer are sequentially formed on a target layer. The undoped polysilicon layer is patterned to form a polysilicon pattern. A first etching process is performed by using the polysilicon pattern as a mask to remove a portion of the core layer to form a core pattern. A second etching process is performed to remove the polysilicon pattern. An atomic layer deposition (ALD) process is performed to form a spacer material on the core pattern and the doped polysilicon layer. A portion of the spacer material is removed to form a spacer on a sidewall of the core pattern. A portion of the core pattern and an underlying doped polysilicon are removed.