公开(公告)号：US20070008798A1

公开(公告)日：2007-01-11

申请号：US11175724

申请日：2005-07-06

申请人： Wolfgang Hokenmaier ,  Peter Thwaite

发明人： Wolfgang Hokenmaier ,  Peter Thwaite

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C7/04 ,  G11C11/40615 ,  G11C11/40626

摘要： A self-refresh module includes an oscillator configured to provide a first signal having a first frequency, a trimming divider configured to trim the first signal to provide a second signal having a second frequency, and a temperature sensor configured to sense a temperature of the memory device and provide a temperature signal. The self-refresh module includes a temperature look-up table configured to receive the temperature signal and provide a third signal based on the temperature signal, and a temperature divider configured to provide a self-refresh pulse signal based on the second signal and the third signal.

公开(公告)号：US07292488B2

公开(公告)日：2007-11-06

申请号：US11175724

申请日：2005-07-06

申请人： Wolfgang Hokenmaier ,  Peter Thwaite

发明人： Wolfgang Hokenmaier ,  Peter Thwaite

IPC分类号： G11C7/00 ,  H03L7/00

CPC分类号： G11C11/406 ,  G11C7/04 ,  G11C11/40615 ,  G11C11/40626

摘要： A self-refresh module includes an oscillator configured to provide a first signal having a first frequency, a trimming divider configured to trim the first signal to provide a second signal having a second frequency, and a temperature sensor configured to sense a temperature of the memory device and provide a temperature signal. The self-refresh module includes a temperature look-up table configured to receive the temperature signal and provide a third signal based on the temperature signal, and a temperature divider configured to provide a self-refresh pulse signal based on the second signal and the third signal.

摘要翻译： 自刷新模块包括配置成提供具有第一频率的第一信号的振荡器，被配置为修整第一信号以提供具有第二频率的第二信号的微调分频器，以及配置成感测存储器的温度的温度传感器 装置并提供温度信号。 自刷新模块包括配置为接收温度信号并基于温度信号提供第三信号的温度查找表，以及配置为基于第二信号和第三信号提供自刷新脉冲信号的温度分配器 信号。

公开(公告)号：US20070070745A1

公开(公告)日：2007-03-29

申请号：US11240981

申请日：2005-09-29

申请人： Martin Versen ,  Peter Thwaite

发明人： Martin Versen ,  Peter Thwaite

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C29/83

摘要： Embodiments of the present inventions provide a method and apparatus for reducing power consumption of a memory device. In one embodiment, the method includes initiating a precharge operation. The precharge operation includes driving one or more bitlines to a precharge voltage. The method also includes identifying one or more defective wordlines and, during the precharge operation, driving the identified defective wordlines to the precharge voltage.

摘要翻译： 本发明的实施例提供了一种用于降低存储器件的功耗的方法和装置。 在一个实施例中，该方法包括启动预充电操作。 预充电操作包括将一个或多个位线驱动为预充电电压。 该方法还包括识别一个或多个有缺陷的字线，并且在预充电操作期间，将所识别的有缺陷的字线驱动到预充电电压。

公开(公告)号：US06914841B1

公开(公告)日：2005-07-05

申请号：US10768202

申请日：2004-01-30

申请人： Peter Thwaite

发明人： Peter Thwaite

IPC分类号： G11C11/406 ,  G11C7/00

CPC分类号： G11C11/40611 ,  G11C7/18 ,  G11C11/406 ,  G11C11/4097 ,  G11C2211/4061

摘要： A memory device (10) includes an array (12) of memory cells arranged in rows and columns. Preferably, each memory cell includes a pass transistor coupled to a storage capacitor. A row decoder (18) is coupled to rows of memory cells while a column decoder (14) is coupled to columns of the memory cells. A refresh controller (19) is adapted to generate memory cell addresses for array (12) during a refresh sequence. In a preferred embodiment of the present invention, the refresh controller ensures that no shared sense amplifiers (24) are activated during consecutive refresh cycles, allowing a portion or all of the time required for precharging the bitlines to be saved. In a preferred embodiment, consecutive refresh cycles can be located closer together in time because a second refresh cycle may be initiated prior to the completion of a first refresh cycle.

摘要翻译： 存储器件（10）包括以行和列布置的存储单元阵列（12）。 优选地，每个存储单元包括耦合到存储电容器的传输晶体管。 行解码器（18）耦合到行存储器单元，而列解码器（14）耦合到存储器单元的列。 刷新控制器（19）适于在刷新序列期间产生阵列（12）的存储单元地址。 在本发明的优选实施例中，刷新控制器确保在连续的刷新周期期间没有激活共享读出放大器（24），从而允许节省预充电所需的时间部分或全部时间。 在优选实施例中，连续的刷新周期可以在时间上更靠近在一起，因为可以在完成第一刷新周期之前启动第二刷新周期。

公开(公告)号：US07405986B2

公开(公告)日：2008-07-29

申请号：US11240981

申请日：2005-09-29

申请人： Martin Versen ,  Peter Thwaite

发明人： Martin Versen ,  Peter Thwaite

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C29/83

摘要： A method and apparatus for reducing power consumption of a memory device. The method includes initiating a precharge operation. The precharge operation includes driving one or more bitlines to a precharge voltage. The method also includes identifying one or more defective wordlines and, during the precharge operation, driving the identified defective word lines to the precharge voltage.

摘要翻译： 一种用于降低存储器件功耗的方法和装置。 该方法包括启动预充电操作。 预充电操作包括将一个或多个位线驱动到预充电电压。 该方法还包括识别一个或多个有缺陷的字线，并且在预充电操作期间，将所识别的有缺陷的字线驱动到预充电电压。

公开(公告)号：US20070200571A1

公开(公告)日：2007-08-30

申请号：US11354969

申请日：2006-02-16

申请人： Kevin Quinn ,  Peter Thwaite

发明人： Kevin Quinn ,  Peter Thwaite

IPC分类号： G01R31/02

CPC分类号： G01R31/31926 ,  G01R31/026

摘要： Verifying good electrical contact between pads of multiple circuit dies and a probe card or test device, where the driver channels of the test device or probe card device are connected in parallel to corresponding contacts on the circuit dies. Each of a plurality of test device or probe card device driver channels are connected to a corresponding one of a plurality of contacts on each of the plurality of circuit dies such that each test device driver channel is shared among a corresponding contact on each of said plurality of circuit dies. Logic circuitry on each chip connects each of the plurality of contacts to at least one designated contact to output from the device via said at least one designated contact a voltage that corresponds to a voltage at one of said plurality of contacts when a voltage is applied to said one of said plurality of contacts. A voltage is applied at the test device driver channel and the voltage on the designated contact of each of the circuit dies that is coupled to said plurality of contacts on the circuit die is evaluated to determine whether contact is made between the test device driver channel pin or terminal (either directly or via or probe card) and the corresponding contact on each of said plurality of circuit dies.

摘要翻译： 验证多个电路管芯的焊盘和探针卡或测试装置之间的良好的电接触，其中测试装置或探针卡装置的驱动器通道与电路管芯上的相应触点并联连接。 多个测试装置或探针卡装置驱动器通道中的每一个连接到多个电路管芯中的每一个上的多个触点中的对应的一个触点，使得每个测试装置驱动器通道在所述多个电路模块的每一个上的对应触点之间共享 的电路模具。 每个芯片上的逻辑电路将多个触点中的每一个连接到至少一个指定触点，以经由所述至少一个指定触点从所述器件输出对应于当施加电压时的所述多个触点中的一个上的电压的电压 所述多个触点中的一个。 在测试装置驱动器通道处施加电压，并且评估耦合到电路管芯上的所述多个触点的每个电路管芯的指定触点上的电压，以确定是否在测试装置驱动器通道引脚 或终端（直接或通过或探针卡）以及所述多个电路管芯中的每一个上的对应接触件。

公开(公告)号：US06534369B2

公开(公告)日：2003-03-18

申请号：US10062755

申请日：2002-01-31

申请人： Peter Thwaite ,  Jochen Beintner

发明人： Peter Thwaite ,  Jochen Beintner

IPC分类号： H01L21336

CPC分类号： H01L29/1033 ,  H01L21/76235

摘要： An Insulated Gate Field Effect Transistor (IGFET), fabricated using Shallow Trench Isolation (STI), has an edge of a channel region of the IGFET which has a curved shape with a controlled radius of curvature so as to reduce the electric field at the edge of the channel region. A method of controlling the shape of the edge of the channel region is to limit the supply of oxygen to the region at the edge of the channel region during the oxidation process when the side walls of the silicon island, in which the transistor will be formed, are initially covered with a layer of silicon oxide.

公开(公告)号：US07324396B2

公开(公告)日：2008-01-29

申请号：US11253727

申请日：2005-10-20

申请人： Peter Thwaite

发明人： Peter Thwaite

IPC分类号： G11C7/02

CPC分类号： G11C7/18 ,  G11C7/06 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/005 ,  G11C2211/4013

摘要： A semiconductor memory device is provided that uses a single wordline to access both storage cells of a so-called twin cell. A memory device comprises a plurality of wordlines and a plurality of bitlines in an array, with a plurality of storage cells at certain intersections of wordlines and bitlines. A plurality of sense amplifiers are provided, each of which is connected to at least a first pair of bitlines to detect a voltage difference on the bitlines caused by the charge from a twin storage cell comprised of first and second storage cells at the intersection of a single wordline with said first pair of bitlines, respectively. As a result, each cell of a twin storage cell can be accessed with a single wordline.

摘要翻译： 提供一种使用单个字线访问所谓的双胞胎的两个存储单元的半导体存储器件。 存储器件包括阵列中的多个字线和多个位线，在字线和位线的某些交叉处具有多个存储单元。 提供了多个读出放大器，每个读出放大器连接到至少第一对位线，以检测由在第一和第二存储单元组成的双存储单元的电荷引起的位线上的电压差， 分别具有所述第一对位线的单字线。 因此，双存储单元的每个单元可以用单个字线访问。

公开(公告)号：US20070091699A1

公开(公告)日：2007-04-26

申请号：US11253727

申请日：2005-10-20

申请人： Peter Thwaite

发明人： Peter Thwaite

IPC分类号： G11C7/02

CPC分类号： G11C7/18 ,  G11C7/06 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/005 ,  G11C2211/4013

摘要： A semiconductor memory device is provided that uses a single wordline to access both storage cells of a so-called twin cell. A memory device comprises a plurality of wordlines and a plurality of bitlines in an array, with a plurality of storage cells at certain intersections of wordlines and bitlines. A plurality of sense amplifiers are provided, each of which is connected to at least a first pair of bitlines to detect a voltage difference on the bitlines caused by the charge from a twin storage cell comprised of first and second storage cells at the intersection of a single wordline with said first pair of bitlines, respectively. As a result, each cell of a twin storage cell can be accessed with a single wordline.

摘要翻译： 提供一种使用单个字线访问所谓的双胞胎的两个存储单元的半导体存储器件。 存储器件包括阵列中的多个字线和多个位线，在字线和位线的某些交叉处具有多个存储单元。 提供了多个读出放大器，每个读出放大器连接到至少第一对位线，以检测由在第一和第二存储单元组成的双存储单元的电荷引起的位线上的电压差， 分别具有所述第一对位线的单字线。 结果，双存储单元的每个单元可以用单个字线访问。

公开(公告)号：US06579768B2

公开(公告)日：2003-06-17

申请号：US10066184

申请日：2002-01-31

申请人： Peter Thwaite ,  Jochen Beintner

发明人： Peter Thwaite ,  Jochen Beintner

IPC分类号： H01L21336

CPC分类号： H01L29/1033 ,  H01L21/76235

摘要： An Insulated Gate Field Effect Transistor (IGFET), fabricated using Shallow Trench Isolation (STI), has an edge of a channel region of the IGFET which has a curved shape with a controlled radius of curvature so as to reduce the electric field at the edge of the channel region. A method of controlling the shape of the edge of the channel region is to limit the supply of oxygen to the region at the edge of the channel region during the oxidation process when the side walls of the silicon island, in which the transistor will be formed, are initially covered with a layer of silicon oxide.