公开(公告)号：US07256441B2

公开(公告)日：2007-08-14

申请号：US11100500

申请日：2005-04-07

Applicant: Woo-Tag Kang ,  Jungwon Suh

Inventor： Woo-Tag Kang ,  Jungwon Suh

IPC: H01L29/76

CPC classification number: H01L29/66621 ,  H01L27/10876

Abstract: A dynamic random access memory (DRAM) cell structure (and method for making a DRAM cell structure) that is more suitable than current DRAM structures for implementation in ever decreasing semiconductor fabrication geometries. The DRAM cell structure comprises a deep trench (DT) capacitor formed in a substrate. A recess is formed in the substrate proximate the deep trench capacitor. A gate is formed that extends into the recess but does not completely occupy the recess. A source is formed in the substrate in a region beneath the recess. A drain is formed in the substrate in a region laterally and vertically offset from the source. A channel between the source and drain is created beneath the gate along a side wall of the recess. Thus, the depth of the recess determines the length of the channel region. With this DRAM cell structure, it is easier to avoid the high doping concentration issue and the short channel effect. Consequently, this DRAM cell structure can be employed with smaller fabrication technologies.

Abstract translation: 一种动态随机存取存储器（DRAM）单元结构（以及用于制造DRAM单元结构的方法）比当前的DRAM结构更适合于在不断降低的半导体制造几何中实现。 DRAM单元结构包括形成在衬底中的深沟槽（DT）电容器。 在靠近深沟槽电容器的衬底中形成凹部。 形成延伸到凹部中但不完全占据凹部的浇口。 在凹陷下方的区域中的基底中形成源。 在从源极侧向和垂直偏移的区域中在衬底中形成漏极。 源极和漏极之间的通道沿着凹槽的侧壁在栅极下方产生。 因此，凹槽的深度决定了通道区域的长度。 利用这种DRAM单元结构，更容易避免高掺杂浓度问题和短沟道效应。 因此，这种DRAM单元结构可以采用较小的制造技术。

公开(公告)号：US20060228861A1

公开(公告)日：2006-10-12

申请号：US11100500

申请日：2005-04-07

Applicant: Woo-Tag Kang ,  Jungwon Suh

Inventor： Woo-Tag Kang ,  Jungwon Suh

IPC: H01L21/336

CPC classification number: H01L29/66621 ,  H01L27/10876

Abstract: A dynamic random access memory (DRAM) cell structure (and method for making a DRAM cell structure) that is more suitable than current DRAM structures for implementation in ever decreasing semiconductor fabrication geometries. The DRAM cell structure comprises a deep trench (DT) capacitor formed in a substrate. A recess is formed in the substrate proximate the deep trench capacitor. A gate is formed that extends into the recess but does not completely occupy the recess. A source is formed in the substrate in a region beneath the recess. A drain is formed in the substrate in a region laterally and vertically offset from the source. A channel between the source and drain is created beneath the gate along a side wall of the recess. Thus, the depth of the recess determines the length of the channel region. With this DRAM cell structure, it is easier to avoid the high doping concentration issue and the short channel effect. Consequently, this DRAM cell structure can be employed with smaller fabrication technologies.

Abstract translation: 一种动态随机存取存储器（DRAM）单元结构（以及用于制造DRAM单元结构的方法）比当前的DRAM结构更适合于在不断降低的半导体制造几何中实现。 DRAM单元结构包括形成在衬底中的深沟槽（DT）电容器。 在靠近深沟槽电容器的衬底中形成凹部。 形成延伸到凹部中但不完全占据凹部的浇口。 在凹陷下方的区域中的基底中形成源。 在从源极侧向和垂直偏移的区域中在衬底中形成漏极。 源极和漏极之间的通道沿着凹槽的侧壁在栅极下方产生。 因此，凹槽的深度决定了通道区域的长度。 利用这种DRAM单元结构，更容易避免高掺杂浓度问题和短沟道效应。 因此，这种DRAM单元结构可以采用较小的制造技术。

公开(公告)号：US07439591B2

公开(公告)日：2008-10-21

申请号：US10958464

申请日：2004-10-05

Applicant: Woo-Tag Kang

Inventor： Woo-Tag Kang

IPC: H01L23/62 ,  H01L27/14

CPC classification number: G11C11/40626 ,  G11C7/04 ,  G11C11/406 ,  H01L27/0214 ,  H01L27/0248 ,  H01L27/0629 ,  H01L27/10897 ,  H01L29/0692 ,  H01L29/861 ,  H01L29/868

Abstract: Method, apparatus, and article of manufacture for a diode defined by a portion of a gate layer of an integrated circuit. Illustrative, non-limiting embodiments of the invention are provided, including a temperature compensated DRAM, a temperature compensated CPU, a temperature compensated logic circuit and other on-chip temperature sensor applications.

Abstract translation: 用于由集成电路的栅极层的一部分限定的二极管的方法，装置和制造。 提供了本发明的说明性的非限制性实施例，包括温度补偿DRAM，温度补偿CPU，温度补偿逻辑电路和其它片上温度传感器应用。

公开(公告)号：US06930357B2

公开(公告)日：2005-08-16

申请号：US10463023

申请日：2003-06-16

Applicant: Woo-Tag Kang

Inventor： Woo-Tag Kang

IPC: H01L21/336 ,  H01L21/74 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/12 ,  H01L29/10 ,  H01L31/0392

CPC classification number: H01L27/1203 ,  H01L21/743 ,  H01L21/84 ,  H01L27/10867 ,  H01L27/10873 ,  H01L29/1087 ,  H01L29/66651

Abstract: A silicon on insulator shaped structure formed to reduce floating body effect comprises a T-shaped active structure and a body contact for back bias. Etching a T-shape through two layers of oxide will form the T-shaped active areas. A back bias is formed when a metal line is dropped through the SOI structure and reaches a contact plug. This contact plug is doped with N+ or P+ dopant and is embedded in a Si substrate. The T-active shaped structure is used to reduce the short channel effects and junction capacitance that normally hinder the effectiveness of bulk transistors. The back bias is used as a conduit for generated holes to leave the SOI transistor area thus greatly reducing the floating effects generally associated with SOI structures.

Abstract translation: 形成为减少浮体效应而形成的绝缘体上的绝缘体结构包括T形有源结构和用于背偏的身体接触。 通过两层氧化物蚀刻T形将形成T形有源区。 当金属线通过SOI结构落下并到达接触塞时，形成背偏压。 该接触插塞掺杂有N +或P +掺杂剂并且嵌入Si衬底中。 T形有源形状结构用于减少通常阻碍体晶体管效率的短沟道效应和结电容。 背偏压用作产生的孔的导管，以离开SOI晶体管区域，从而大大降低了通常与SOI结构相关联的浮动效应。

公开(公告)号：US06537885B1

公开(公告)日：2003-03-25

申请号：US10142537

申请日：2002-05-09

Applicant: Woo-Tag Kang ,  Kil-Ho Lee

Inventor： Woo-Tag Kang ,  Kil-Ho Lee

IPC: H01L21336

CPC classification number: H01L29/66628 ,  H01L29/7834

Abstract: A method of manufacturing a transistor by using two layers of a silicon epitaxial layer is disclosed. In the first step of the manufacturing process, a spacer is formed around gate structures. Then, a first silicon epitaxial layer is grown on the wafer. Then, a second spacer is deposited and then etched, such that the second spacer remains around a gate structure. Next a second silicon epitaxial layer is grown on the first silicon epitaxial layer, and the second spacer is etched from around the gate structure. After etching the first oxide spacer, ions are implanted at a first energy level to form four junctions. Then a third spacer is deposited and etched, so that the third spacer remains around the gate structures. Then ions are implanted at a second energy level to form two more junctions, each of these two junctions being located between two of the earlier formed junctions. The junctions and the gate structures provide a transistor structure. The resulting transistor has a good short channel effect because the junction depths are preferably all aligned. It also has good drive current because the junctions created by ion implantation at a second energy level have low parasitic resistance.

Abstract translation: 公开了通过使用两层硅外延层制造晶体管的方法。 在制造工艺的第一步骤中，在栅极结构周围形成间隔物。 然后，在晶片上生长第一硅外延层。 然后，沉积第二间隔物，然后蚀刻，使得第二间隔物保留在栅极结构周围。 接下来，在第一硅外延层上生长第二硅外延层，并且从栅极结构周围蚀刻第二间隔物。 在蚀刻第一氧化物间隔物之后，以第一能级注入离子以形成四个结。 然后沉积和蚀刻第三间隔物，使得第三间隔物保留在栅极结构周围。 然后离子以第二能级注入以形成两个结，这两个结中的每一个位于两个较早形成的结之间。 结和栅极结构提供晶体管结构。 所得到的晶体管具有良好的短沟道效应，因为结深度优选地全部对准。 它还具有良好的驱动电流，因为在第二能级处由离子注入产生的结具有低寄生电阻。

公开(公告)号：US20060071257A1

公开(公告)日：2006-04-06

申请号：US10958464

申请日：2004-10-05

Applicant: Woo-Tag Kang

Inventor： Woo-Tag Kang

IPC: H01L29/94

CPC classification number: G11C11/40626 ,  G11C7/04 ,  G11C11/406 ,  H01L27/0214 ,  H01L27/0248 ,  H01L27/0629 ,  H01L27/10897 ,  H01L29/0692 ,  H01L29/861 ,  H01L29/868

Abstract: Method, apparatus, and article of manufacture for a diode defined by a portion of a gate layer of an integrated circuit. Illustrative, non-limiting embodiments of the invention are provided, including a temperature compensated DRAM, a temperature compensated CPU, a temperature compensated logic circuit and other on-chip temperature sensor applications.

Abstract translation: 用于由集成电路的栅极层的一部分限定的二极管的方法，装置和制造。 提供了本发明的说明性的非限制性实施例，包括温度补偿DRAM，温度补偿CPU，温度补偿逻辑电路和其它片上温度传感器应用。

公开(公告)号：US06326270B1

公开(公告)日：2001-12-04

申请号：US09419836

申请日：1999-10-15

Applicant: Kang-Yoon Lee ,  Woo-Tag Kang ,  Jeong-Seok Kim ,  Yoo-Cheol Shin

Inventor： Kang-Yoon Lee ,  Woo-Tag Kang ,  Jeong-Seok Kim ,  Yoo-Cheol Shin

IPC: H01L21336

CPC classification number: H01L21/76816 ,  H01L21/76805 ,  H01L21/76897 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897

Abstract: Methods of forming integrated circuit memory devices may include steps to form memory cell access transistors therein. These steps may include steps to form a gate line on a semiconductor substrate and then implant dopants of first conductivity type into the semiconductor substrate to define a self-aligned impurity region therein. A spacer layer of a first material is then formed on a sidewall and upper surface of the gate line. An interlayer insulating layer of a second material is then formed on the spacer layer. A series of selective etching steps are then performed using different etchants. For example, a step is performed to selectively etch the interlayer insulating layer to define a contact hole therein, using the spacer layer as an etching mask to protect the gate line from etching damage. A selective etching step is then performed to convert the spacer layer into a sidewall spacer on the sidewall of the gate line. This etching step is performed using the interlayer insulating layer as an etching mask. A conductive plug (e.g., bit line plug) is then formed in the contact hole. This conductive plug forms an ohmic contact with the impurity region.

Abstract translation: 形成集成电路存储器件的方法可以包括在其中形成存储单元存取晶体管的步骤。 这些步骤可以包括在半导体衬底上形成栅极线，然后将第一导电类型的掺杂剂注入到半导体衬底中以限定其中的自对准杂质区的步骤。 然后在栅极线的侧壁和上表面上形成第一材料的间隔层。 然后在间隔层上形成第二材料的层间绝缘层。 然后使用不同的蚀刻剂执行一系列选择性蚀刻步骤。 例如，使用间隔层作为蚀刻掩模来执行步骤以选择性地蚀刻层间绝缘层以限定其中的接触孔，以保护栅极线免受蚀刻损伤。 然后执行选择性蚀刻步骤以将间隔层转换成栅极线的侧壁上的侧壁间隔物。 该蚀刻步骤使用层间绝缘层作为蚀刻掩模进行。 然后在接触孔中形成导电插塞（例如，位线插头）。 该导电插塞与杂质区形成欧姆接触。

公开(公告)号：US6080622A

公开(公告)日：2000-06-27

申请号：US281575

申请日：1999-03-30

Applicant: Woo-Tag Kang

Inventor： Woo-Tag Kang

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/10852

Abstract: Disclosed is an improved method for fabricating a DRAM cell capacitor. The method includes the steps of depositing a first insulating layer over a semiconductor substrate having a field effect transistor, etching the first insulating layer and forming a contact hole therein to one of two source/drain areas of the field effect transistor, filling the contact hole with a first conductive layer thereby to form a contact plug, depositing a thin second conductive layer and a relatively thick second insulating layer on the contact plug and the semiconductor substrate, etching the second insulating layer using a capacitor mask and forming an opening in the second insulating layer to the second conductive layer at a position opposite to underlying the contact plug, filling the opening with a third conductive layer thereby to form a storage node pattern, removing the second insulating layer outside of the storage node pattern, etching the second conductive layer until the first insulating layer outside of the storage node pattern is exposed thereby to form a storage node.

Abstract translation: 公开了一种用于制造DRAM单元电容器的改进方法。 该方法包括以下步骤：在具有场效应晶体管的半导体衬底上沉积第一绝缘层，蚀刻第一绝缘层并在场效应晶体管的两个源极/漏极区之一上形成接触孔，填充接触孔 与第一导电层形成接触塞，在接触插塞和半导体衬底上沉积薄的第二导电层和相对较厚的第二绝缘层，使用电容器掩模蚀刻第二绝缘层，并在第二导电层中形成开口 将绝缘层与位于接触插塞下方的位置相对的第二导电层，用第三导电层填充开口，从而形成存储节点图案，去除存储节点图案之外的第二绝缘层，蚀刻第二导电层 直到存储节点图案外部的第一绝缘层暴露，从而形成存储 ge节点。