公开(公告)号：US07679085B2

公开(公告)日：2010-03-16

申请号：US11646241

申请日：2006-12-28

申请人： Woong Gi Jun ,  Gee Sung Chae ,  Jae Seok Heo

发明人： Woong Gi Jun ,  Gee Sung Chae ,  Jae Seok Heo

IPC分类号： H01L29/04 ,  H01L35/24

CPC分类号： H01L29/78669 ,  H01L27/1248 ,  H01L27/1292 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66765 ,  H01L51/0533 ,  H01L51/0545

摘要： A method for fabricating a thin film transistor (TFT) on a substrate includes forming a gate electrode; forming a semiconductor layer being insulated from the gate electrode and partially overlapped with the gate electrode; sequentially forming first and second gate insulating layers between the gate electrode and the semiconductor layer, wherein the first gate insulating layer is formed of a material different from the second gate insulating layer and at least one of the first and second gate insulating layers includes a sol-compound; and forming source and drain electrodes at both sides of the semiconductor layer.

摘要翻译： 在衬底上制造薄膜晶体管（TFT）的方法包括：形成栅电极; 形成与所述栅电极绝缘并与所述栅电极部分重叠的半导体层; 在栅电极和半导体层之间依次形成第一栅极绝缘层和第二栅极绝缘层，其中第一栅极绝缘层由不同于第二栅极绝缘层的材料形成，并且第一和第二栅极绝缘层中的至少一个包括溶胶 -复合; 以及在半导体层的两侧形成源极和漏极。

公开(公告)号：US08129233B2

公开(公告)日：2012-03-06

申请号：US12656316

申请日：2010-01-25

申请人： Woong Gi Jun ,  Gee Sung Chae ,  Jae Seok Heo

发明人： Woong Gi Jun ,  Gee Sung Chae ,  Jae Seok Heo

IPC分类号： H01L21/00

CPC分类号： H01L29/78669 ,  H01L27/1248 ,  H01L27/1292 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66765 ,  H01L51/0533 ,  H01L51/0545

摘要： A method for fabricating a thin film transistor (TFT) on a substrate includes forming a gate electrode; forming a semiconductor layer being insulated from the gate electrode and partially overlapped with the gate electrode; sequentially forming first and second gate insulating layers between the gate electrode and the semiconductor layer, wherein the first gate insulating layer is formed of a material different from the second gate insulating layer and at least one of the first and second gate insulating layers includes a sol-compound; and forming source and drain electrodes at both sides of the semiconductor layer.

摘要翻译： 在衬底上制造薄膜晶体管（TFT）的方法包括：形成栅电极; 形成与所述栅电极绝缘并与所述栅电极部分重叠的半导体层; 在栅电极和半导体层之间依次形成第一栅极绝缘层和第二栅极绝缘层，其中第一栅极绝缘层由不同于第二栅极绝缘层的材料形成，并且第一和第二栅极绝缘层中的至少一个包括溶胶 -复合; 以及在半导体层的两侧形成源极和漏极。

公开(公告)号：US08062924B2

公开(公告)日：2011-11-22

申请号：US12656507

申请日：2010-02-01

申请人： Gee Sung Chae ,  Jae Seok Heo ,  Woong Gi Jun

发明人： Gee Sung Chae ,  Jae Seok Heo ,  Woong Gi Jun

IPC分类号： H01L51/40

CPC分类号： H01L29/4908 ,  H01L29/66765

摘要： A method for fabricating a TFT on a substrate includes forming a gate electrode; forming a semiconductor layer insulated from the gate electrode and partially overlapped with the gate electrode; forming a gate insulating layer between the gate electrode and the semiconductor layer, the gate insulating layer including a sol-gel compound; and forming source and drain electrodes at both sides of the semiconductor layer.

摘要翻译： 在衬底上制造TFT的方法包括：形成栅电极; 形成与栅电极绝缘并与栅电极部分重叠的半导体层; 在所述栅电极和所述半导体层之间形成栅极绝缘层，所述栅绝缘层包括溶胶 - 凝胶化合物; 以及在半导体层的两侧形成源极和漏极。

公开(公告)号：US20100136756A1

公开(公告)日：2010-06-03

申请号：US12656507

申请日：2010-02-01

申请人： Gee Sung Chae ,  Jae Seok Heo ,  Woong Gi Jun

发明人： Gee Sung Chae ,  Jae Seok Heo ,  Woong Gi Jun

IPC分类号： H01L21/336

CPC分类号： H01L29/4908 ,  H01L29/66765

摘要： A method for fabricating a TFT on a substrate includes forming a gate electrode; forming a semiconductor layer insulated from the gate electrode and partially overlapped with the gate electrode; forming a gate insulating layer between the gate electrode and the semiconductor layer, the gate insulating layer including a sol-gel compound; and forming source and drain electrodes at both sides of the semiconductor layer.

公开(公告)号：US07683367B2

公开(公告)日：2010-03-23

申请号：US11644981

申请日：2006-12-26

申请人： Gee Sung Chae ,  Jae Seok Heo ,  Woong Gi Jun

发明人： Gee Sung Chae ,  Jae Seok Heo ,  Woong Gi Jun

IPC分类号： H01L35/24 ,  H01L51/00

CPC分类号： H01L29/4908 ,  H01L29/66765

摘要： A method for fabricating a TFT on a substrate includes forming a gate electrode; forming a semiconductor layer insulated from the gate electrode and partially overlapped with the gate electrode; forming a gate insulating layer between the gate electrode and the semiconductor layer, the gate insulating layer including a sol-gel compound; and forming source and drain electrodes at both sides of the semiconductor layer.

摘要翻译： 在衬底上制造TFT的方法包括：形成栅电极; 形成与栅电极绝缘并与栅电极部分重叠的半导体层; 在所述栅电极和所述半导体层之间形成栅极绝缘层，所述栅绝缘层包括溶胶 - 凝胶化合物; 以及在半导体层的两侧形成源极和漏极。

公开(公告)号：US20080001150A1

公开(公告)日：2008-01-03

申请号：US11644981

申请日：2006-12-26

申请人： Gee Sung Chae ,  Jae Seok Heo ,  Woong Gi Jun

发明人： Gee Sung Chae ,  Jae Seok Heo ,  Woong Gi Jun

IPC分类号： H01L29/04

CPC分类号： H01L29/4908 ,  H01L29/66765

摘要： A method for fabricating a TFT on a substrate includes forming a gate electrode; forming a semiconductor layer insulated from the gate electrode and partially overlapped with the gate electrode; forming a gate insulating layer between the gate electrode and the semiconductor layer, the gate insulating layer including a sol-gel compound; and forming source and drain electrodes at both sides of the semiconductor layer.

摘要翻译： 在衬底上制造TFT的方法包括：形成栅电极; 形成与栅电极绝缘并与栅电极部分重叠的半导体层; 在所述栅电极和所述半导体层之间形成栅极绝缘层，所述栅绝缘层包括溶胶 - 凝胶化合物; 以及在半导体层的两侧形成源极和漏极。

公开(公告)号：US07420213B2

公开(公告)日：2008-09-02

申请号：US11410212

申请日：2006-04-25

申请人： Gee Sung Chae ,  Jae Seok Heo

发明人： Gee Sung Chae ,  Jae Seok Heo

IPC分类号： H01L27/14 ,  H01L29/04 ,  H01L29/15 ,  H01L31/036

CPC分类号： H01L29/4908 ,  H01L27/124

摘要： A thin film transistor array substrate is provided. The thin film transistor array substrate includes a substrate; a gate pattern of a gate electrode and a gate line connected to the gate electrode on the substrate; a main gate insulating film formed of an organic material to cover the gate pattern; a semiconductor pattern overlapping the gate line such that the main gate insulating film is disposed between semiconductor patter and the gate line; a source/drain pattern on the semiconductor pattern. The source/drain pattern has a data line crossing the gate line with the main gate insulating film therebetween, a source electrode and a drain electrode, Here, the source electrode, the drain electrode and the semiconductor pattern define a thin film transistor disposed at the intersection between the gate line and the data line. The thin film transistor array substrate further includes a protective film defining a contact hole at a portion of the drain electrode; a pixel electrode contacting the drain electrode through the contact hole; and a sub gate insulating pattern disposed between the gate pattern and the main gate insulating film overlapping the gate pattern. The sub gate insulating pattern includes a ferroelectric material.

摘要翻译： 提供薄膜晶体管阵列基板。 薄膜晶体管阵列基板包括基板; 栅电极的栅极图案和与基板上的栅电极连接的栅极线; 由有机材料形成以覆盖栅极图案的主栅极绝缘膜; 半导体图案与栅极线重叠，使得主栅极绝缘膜设置在半导体图案和栅极线之间; 半导体图案上的源极/漏极图案。 源极/漏极图案具有与栅极线与主栅极绝缘膜交叉的数据线，源电极和漏电极。这里，源电极，漏电极和半导体图案限定了设置在 栅极线与数据线之间的交点。 薄膜晶体管阵列基板还包括限定漏电极的一部分处的接触孔的保护膜; 通过所述接触孔与所述漏电极接触的像素电极; 以及设置在与栅极图案重叠的栅极图案和主栅极绝缘膜之间的子栅极绝缘图案。 子栅绝缘图案包括铁电材料。

公开(公告)号：US08551825B2

公开(公告)日：2013-10-08

申请号：US13155972

申请日：2011-06-08

申请人： Bo Hyun Lee ,  Jae Seok Heo ,  Woong Gi Jun

发明人： Bo Hyun Lee ,  Jae Seok Heo ,  Woong Gi Jun

IPC分类号： H01L21/00

CPC分类号： H01L27/1248 ,  G02F1/136227

摘要： A thin film transistor (TFT) array substrate and a method for fabricating the thin film transistor (TFT) array substrate is disclosed, wherein a passivation layer is directly subjected to exposing and patterning processes without using any photoresist, thereby simplifying the fabrication process and ensuring reduced preparation costs. In particular, the method comprises a thin film transistor (TFT) array comprising: forming a gate line and a gate electrode on a substrate; forming a semiconductor layer to be insulated from the gate electrode, and overlapped with a portion of the gate electrode; forming a source electrode and a drain electrode on both sides of the semiconductor layer, respectively, while forming a data line intersecting with the gate line; forming a passivation layer over an entire upper surface of the substrate including the source electrode and the drain electrode using a sol compound of a metal alkoxide having a photosensitive group X and a silicon alkoxide having a photosensitive group Y; light-exposing and developing the passivation layer to form a contact hole through which the drain electrode is exposed; and forming a pixel electrode to be in contact with the drain electrode through the contact hole.

摘要翻译： 公开了薄膜晶体管（TFT）阵列基板和制造薄膜晶体管（TFT）阵列基板的方法），其中钝化层直接进行曝光和图案化处理，而不使用任何光致抗蚀剂，从而简化制造工艺并确保 降低准备成本。 特别地，该方法包括薄膜晶体管（TFT）阵列，其包括：在基板上形成栅极线和栅电极; 形成与所述栅电极绝缘的半导体层，并与所述栅电极的一部分重叠; 在形成与栅极线相交的数据线的同时分别在半导体层的两侧形成源电极和漏电极; 使用具有感光性基团X的金属醇盐和具有感光性基团Y的硅醇盐的溶胶化合物，在包含源电极和漏电极的基板的整个上表面上形成钝化层; 曝光和显影钝化层以形成漏电极暴露的接触孔; 以及通过接触孔形成与漏电极接触的像素电极。

公开(公告)号：US20110237010A1

公开(公告)日：2011-09-29

申请号：US13155972

申请日：2011-06-08

申请人： Bo Hyun Lee ,  Jae Seok Heo ,  Woong Gi Jun

发明人： Bo Hyun Lee ,  Jae Seok Heo ,  Woong Gi Jun

IPC分类号： H01L33/62

CPC分类号： H01L27/1248 ,  G02F1/136227

摘要： A thin film transistor (TFT) array substrate and a method for fabricating the thin film transistor (TFT) array substrate is disclosed, wherein a passivation layer is directly subjected to exposing and patterning processes without using any photoresist, thereby simplifying the fabrication process and ensuring reduced preparation costs. In particular, the method comprises a thin film transistor (TFT) array comprising: forming a gate line and a gate electrode on a substrate; forming a semiconductor layer to be insulated from the gate electrode, and overlapped with a portion of the gate electrode; forming a source electrode and a drain electrode on both sides of the semiconductor layer, respectively, while forming a data line intersecting with the gate line; forming a passivation layer over an entire upper surface of the substrate including the source electrode and the drain electrode using a sol compound of a metal alkoxide having a photosensitive group X and a silicon alkoxide having a photosensitive group Y; light-exposing and developing the passivation layer to form a contact hole through which the drain electrode is exposed; and forming a pixel electrode to be in contact with the drain electrode through the contact hole.

摘要翻译： 公开了薄膜晶体管（TFT）阵列基板和制造薄膜晶体管（TFT）阵列基板的方法），其中钝化层直接进行曝光和图案化处理，而不使用任何光致抗蚀剂，从而简化制造工艺并确保 降低准备成本。 特别地，该方法包括薄膜晶体管（TFT）阵列，其包括：在基板上形成栅极线和栅电极; 形成与所述栅电极绝缘的半导体层，并与所述栅电极的一部分重叠; 在形成与栅极线相交的数据线的同时分别在半导体层的两侧形成源电极和漏电极; 使用具有感光性基团X的金属醇盐和具有感光性基团Y的硅醇盐的溶胶化合物，在包含源电极和漏电极的基板的整个上表面上形成钝化层; 曝光和显影钝化层以形成漏电极暴露的接触孔; 以及通过接触孔形成与漏电极接触的像素电极。

公开(公告)号：US20080001152A1

公开(公告)日：2008-01-03

申请号：US11646718

申请日：2006-12-27

申请人： Bo Hyun Lee ,  Jae Seok Heo ,  Woong Gi Jun

发明人： Bo Hyun Lee ,  Jae Seok Heo ,  Woong Gi Jun

IPC分类号： H01L29/04

CPC分类号： H01L27/1248 ,  G02F1/136227

摘要： A thin film transistor (TFT) array substrate and a method for fabricating the thin film transistor (TFT) array substrate is disclosed, wherein a passivation layer is directly subjected to exposing and patterning processes without using any photoresist, thereby simplifying the fabrication process and ensuring reduced preparation costs. In particular, the method comprises a thin film transistor (TFT) array comprising: forming a gate line and a gate electrode on a substrate; forming a semiconductor layer to be insulated from the gate electrode, and overlapped with a portion of the gate electrode; forming a source electrode and a drain electrode on both sides of the semiconductor layer, respectively, while forming a data line intersecting with the gate line; forming a passivation layer over an entire upper surface of the substrate including the source electrode and the drain electrode using a sol compound of a metal alkoxide having a photosensitive group X and a silicon alkoxide having a photosensitive group Y; light-exposing and developing the passivation layer to form a contact hole through which the drain electrode is exposed; and forming a pixel electrode to be in contact with the drain electrode through the contact hole.

摘要翻译： 公开了薄膜晶体管（TFT）阵列基板和制造薄膜晶体管（TFT）阵列基板的方法），其中钝化层直接进行曝光和图案化处理，而不使用任何光致抗蚀剂，从而简化制造工艺并确保 降低准备成本。 特别地，该方法包括薄膜晶体管（TFT）阵列，其包括：在基板上形成栅极线和栅电极; 形成与所述栅电极绝缘的半导体层，并与所述栅电极的一部分重叠; 在形成与栅极线相交的数据线的同时分别在半导体层的两侧形成源电极和漏电极; 使用具有感光性基团X的金属醇盐和具有感光性基团Y的硅醇盐的溶胶化合物，在包含源电极和漏电极的基板的整个上表面上形成钝化层; 曝光和显影钝化层以形成漏电极暴露的接触孔; 以及通过接触孔形成与漏电极接触的像素电极。