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    Solving a circuit network in multicore or distributed computing environment
    1.
    发明授权
    Solving a circuit network in multicore or distributed computing environment 有权
    在多核或分布式计算环境中解决电路网

    公开(公告)号：US09471733B1

    公开(公告)日：2016-10-18

    申请号：US14847514

    申请日：2015-09-08

    Applicant: WorldWide Pro Ltd.

    Inventor： William Wai Yan Ho

    IPC: G06F17/50

    CPC classification number: G06F17/5036

    Abstract: Any primitive cells or blocks can be represented physically by a Barycenter compact model, and any black box model can also be physically represented by a Barycenter compact model physically. A hierarchical boundary condition between blocks is formulated by the Barycenter model or Barycenter compact model. Hierarchical boundary condition problems between blocks can be limited within two levels only if using the Barycenter model or Barycenter compact model.

    Abstract translation: 任何原始单元格或块可以通过重心紧凑型模型物理表示，任何黑匣子模型也可以物理地由重心紧凑模型物理地表示。 块之间的分层边界条件由重心模型或重心紧凑模型来制定。 块之间的分层边界条件问题只有在使用Barycenter模型或Barycenter compact模型时才能被限制在两个层次之内。

    Partitioning electronic circuits for simulation on multicore processors
    2.
    发明授权
    Partitioning electronic circuits for simulation on multicore processors 有权
    分离电子电路，用于在多核处理器上进行仿真

    公开(公告)号：US09218441B1

    公开(公告)日：2015-12-22

    申请号：US14557333

    申请日：2014-12-01

    Applicant: Worldwide Pro Ltd.

    Inventor： William Wai Yan Ho

    IPC: G06F17/50

    CPC classification number: G06F17/5036 ,  G06F17/5009

    Abstract: A circuit is simulated by using distributed computing to obtain a real solution. The circuit may be an entire integrated circuit, portion of an integrated circuit, or a circuit block. A circuit simulation technique of the invention generates a system graph, finds a tree, and partitions the tree into two or more subtrees. The technique identifies global links and local links in the graph. Each subtree may be solved individually using distributed, parallel computing (e.g., using multiple processor cores or multiple processors). Using the results for the subtrees, the technique obtains a real solution, branch voltages and currents, for the circuit.

    Abstract translation: 通过使用分布式计算来模拟电路以获得真正的解决方案。 电路可以是整个集成电路，集成电路的一部分或电路块。 本发明的电路模拟技术生成系统图，找到一个树，并将树分成两个或多个子树。 该技术识别图中的全局链接和本地链接。 可以使用分布式并行计算（例如，使用多个处理器核或多个处理器）来单独地解决每个子树。 使用子树的结果，该技术为电路获得实际解决方案，分支电压和电流。

    Partitioning electronic circuits for simulation on multicore processors
    3.
    发明授权
    Partitioning electronic circuits for simulation on multicore processors 有权
    分离电子电路，用于在多核处理器上进行仿真

    公开(公告)号：US08903686B1

    公开(公告)日：2014-12-02

    申请号：US13797523

    申请日：2013-03-12

    Applicant: Worldwide Pro Ltd.

    Inventor： William Wai Yan Ho

    IPC: G06F17/50

    CPC classification number: G06F17/5036 ,  G06F17/5009

    Abstract: A circuit is simulated by using distributed computing to obtain a real solution. The circuit may be an entire integrated circuit, portion of an integrated circuit, or a circuit block. A circuit simulation technique of the invention generates a system graph, finds a tree, and partitions the tree into two or more subtrees. The technique identifies global links and local links in the graph. Each subtree may be solved individually using distributed, parallel computing (e.g., using multiple processor cores or multiple processors). Using the results for the subtrees, the technique obtains a real solution, branch voltages and currents, for the circuit.

    Abstract translation: 通过使用分布式计算来模拟电路以获得真正的解决方案。 电路可以是整个集成电路，集成电路的一部分或电路块。 本发明的电路模拟技术生成系统图，找到一个树，并将树分成两个或多个子树。 该技术识别图中的全局链接和本地链接。 可以使用分布式并行计算（例如，使用多个处理器核或多个处理器）来单独地解决每个子树。 使用子树的结果，该技术为电路获得实际解决方案，分支电压和电流。

    Hierarchical visualization-based analysis of integrated circuits
    5.
    发明授权
    Hierarchical visualization-based analysis of integrated circuits 有权
    集成电路的分层可视化分析

    公开(公告)号：US09286430B1

    公开(公告)日：2016-03-15

    申请号：US14196971

    申请日：2014-03-04

    Applicant: WorldWide Pro Ltd.

    Inventor： William Wai Yan Ho

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5009 ,  G06F17/5068

    Abstract: A system or technique provides for a hierarchical visual-based analysis of electrical integrated circuit system simulation results. A 3D visualization may be used to identify and conduct an analysis of the integrated circuit. An analysis is done on a specific feature of the integrated circuit that is visible in the 3D visualization. The specific feature may be one that is obscured by other layers of the integrated circuit visualization.

    Abstract translation: 系统或技术提供电集成电路系统仿真结果的分层视觉分析。 可以使用3D可视化来识别和进行集成电路的分析。 对3D可视化中可见的集成电路的特定功能进行分析。 具体特征可以是由集成电路可视化的其他层遮蔽的特征。

    Solving a hierarchical circuit network using a barycenter compact model
    6.
    发明授权
    Solving a hierarchical circuit network using a barycenter compact model 有权
    使用重心紧凑型解决分层电路网络

    公开(公告)号：US09111058B1

    公开(公告)日：2015-08-18

    申请号：US14248269

    申请日：2014-04-08

    Applicant: Worldwide Pro Ltd.

    Inventor： William Wai Yan Ho

    IPC: G06F7/60 ,  G06F17/50

    CPC classification number: G06F17/5072 ,  G06F17/5009 ,  G06F17/5036 ,  G06F17/505 ,  G06F17/5081 ,  G06F2217/82

    Abstract: Any primitive cells or blocks can be represented physically by a Barycenter compact model (or Barycenter model), and any black box model can also be physically represented by a Barycenter compact model physically. A hierarchical boundary condition between blocks is formulated by the Barycenter compact model. Hierarchical boundary condition problems between blocks can be limited within two levels only if using the Barycenter compact model.

    Abstract translation: 任何原始单元格或块都可以通过重心紧凑模型（或Barycenter模型）进行物理表示，任何黑盒子模型也可以通过物理上的重心紧凑模型进行物理表示。 块之间的分层边界条件由重心紧凑模型制定。 块之间的分层边界条件问题只能在使用Barycenter compact模型的情况下限制在两个层次之内。

    Validating integrated circuit simulation results
    8.
    发明授权
    Validating integrated circuit simulation results 有权
    验证集成电路仿真结果

    公开(公告)号：US09122837B1

    公开(公告)日：2015-09-01

    申请号：US14271189

    申请日：2014-05-06

    Applicant: Worldwide Pro Ltd.

    Inventor： William Wai Yan Ho

    IPC: G06F17/50

    CPC classification number: G06F17/504 ,  G06F17/5036 ,  G06F17/5081

    Abstract: A technique validates results from a circuit simulation estimation program. The technique determines whether the estimated results satisfy Kirchhoff's current law (KCL), Kirchhoff's voltage laws (KVL), and power conservation for the original circuit. A reporting tool shows the validation results and may be customized by the user. The tool can show in the original circuitry where the estimated results may be inaccurate.

    Abstract translation: 一种技术验证了电路仿真估计程序的结果。 该技术确定估计结果是否满足基尔霍夫电流定律（KCL），基尔霍夫电压定律（KVL）和原始电路的功率守恒。 报告工具显示验证结果，可由用户自定义。 该工具可以在原始电路中显示估计结果可能不准确。

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