公开(公告)号：US20240394552A1

公开(公告)日：2024-11-28

申请号：US18202029

申请日：2023-05-25

Applicant: X DEVELOPMENT LLC

Inventor： Xiaoqing Xu ,  Wenjie Jiang ,  Chia-tung Ho

IPC: G06N3/092

Abstract: The technology provides techniques for optimizing transistor-level placement using a hybrid approach involving reinforcement learning (“RL”) in conjunction with an optimization technique. This can include implementing an iterative RL training process for an integrated circuit to train a RL agent, including the RL agent learning an ordering of transistors for the integrated circuit by placement of one transistor on an encoded grid per iteration. The RL agent iterates until all transistors for the integrated circuit are placed on the encoded grid. Upon placing all the transistors on the encoded grid, one or more processors implement a solver module using the ordering of the transistors as an input. The solver module is configured to perform an optimization to minimize spacing between the transistors. The trained reinforcement learning agent can then be save in memory.

公开(公告)号：US20240176943A1

公开(公告)日：2024-05-30

申请号：US18235437

申请日：2023-08-18

Applicant: X DEVELOPMENT LLC

Inventor： Xiaoqing Xu ,  Herman Schmit ,  Alessandro Tempia Calvino

IPC: G06F30/398 ,  G06F30/31

CPC classification number: G06F30/398 ,  G06F30/31

Abstract: The technology involves the auto-creation of custom standard cells. The process may include receiving specifications for implementing a set of functionalities in an integrated circuit to be fabricated. From this, the system identifies which cells are required to implement the set of functionalities. The identified cells are evaluated against a standard cell library stored in memory to determine which of the cells are not in the standard cell library. The system automatically creates the cells that are not in the standard cell library. The system can then utilize the automatically created cells to fabricate the integrated circuit. Benefits of such an approach include reduced design, development time and improved design quality of results. The resulting new cells may have fewer transistors, less area/power and improved performance than a standard cell from a preexisting library, especially since such standard cells would not necessarily be configurable to perform the desired functions.

公开(公告)号：US20240169134A1

公开(公告)日：2024-05-23

申请号：US18462628

申请日：2023-09-07

Applicant: X DEVELOPMENT LLC

Inventor： Alessandro Tempia Calvino ,  Xiaoqing Xu ,  Herman Schmit

IPC: G06F30/327 ,  G06F17/11 ,  G06F30/337

CPC classification number: G06F30/327 ,  G06F17/11 ,  G06F30/337

Abstract: The technology involves transistor-level synthesis for integrated circuit design and fabrication. According to one aspect, a computer-implemented method performs transistor-level synthesis for an integrated circuit element. This includes generating single-stage transistor networks from Boolean functions, in which each single-stage transistor network is composed of a pulldown network and a pullup network. The single-stage transistor networks are scaled to multi-stage transistor networks to globally optimize for factored form literals. Technology mapping can then be performed based on the factored form literals to generate a circuit design.

公开(公告)号：US20230259689A1

公开(公告)日：2023-08-17

申请号：US17957621

申请日：2022-09-30

Applicant: X Development LLC

Inventor： Xiaoqing Xu ,  Dino Ruic

IPC: G06F30/398 ,  G06F30/394

CPC classification number: G06F30/398 ,  G06F30/394

Abstract: In some embodiments, a computer-implemented method for designing an integrated circuit using transistor placement optimization is provided. A computing system receives a specification for the integrated circuit. The specification includes a netlist describing a plurality of transistors and connections between terminals of the plurality of transistors. The computing system determines an initial location and an orientation on a canvas for each transistor in the plurality of transistors. The computing system uses an objective function based at least in part on the initial locations and the orientations of the plurality of transistors to generate a rough placement having globally optimized locations and orientations for the plurality of transistors. The computing system uses a local refinement technique to optimize the rough placement to generate a fine placement, and uses a routing technique to generate a routing for the fine placement to generate a completed design.