公开(公告)号：US20240274218A1

公开(公告)日：2024-08-15

申请号：US18109744

申请日：2023-02-14

Applicant: XILINX, INC.

Inventor： David TRAN ,  Federico VENINI ,  Sarosh I. AZAD

IPC: G11C29/52 ,  G11C29/02

CPC classification number: G11C29/52 ,  G11C29/022

Abstract: Embodiments herein describe a memory system with a data width (W) that is split into N separate memories each of narrower width W/N. To protect a write enable (WE) signal, the WE signal is toggled and then stored in each of the N memories. For example, toggle circuits can have states that toggle each time the WE signal goes high, indicated that a received data word should be stored in the N memories. A fault on the WE input to any of the N memories results in its stored toggle bit being different from the toggle bits stored in the other N memories. This condition can then be detected upon any subsequent read by checking whether the toggled bits are equal. The memory system can also protect the address and control signals by generating parity bits that are stored in the N memories.

公开(公告)号：US20240160818A1

公开(公告)日：2024-05-16

申请号：US17985735

申请日：2022-11-11

Applicant: XILINX, INC.

Inventor： Federico VENINI ,  David TRAN

IPC: G06F30/33 ,  G06F30/323

CPC classification number: G06F30/33 ,  G06F30/323 ,  G06F2119/02

Abstract: Safety mechanisms are embedded into a System on a Chip (SoC) and are operable to detect faults present in the logic circuitry in the SoC. Various types of faults in logic circuitry can occur, for example, a bit stuck at 0 or 1, or a transient or temporary fault due to radiation impacting the SoC. SoC devices are required to meet certain automotive safety integrity standards. The most stringent automotive safety integrity level requires that 90% of random latent faults are detected in all relevant logic, including all safety mechanism. Examples disclosed include hardware based checkers and hardware or software based pattern generation methods that achieve high online fault coverage in safety mechanism circuitry used for functional safety. A hardware based safety mechanism monitors the logic circuitry during operation. Any time the safety mechanism detects any faults in the logic circuitry, a fault notification is propagated to upstream logic.