公开(公告)号：US20250006694A1

公开(公告)日：2025-01-02

申请号：US18215685

申请日：2023-06-28

Applicant: XILINX, INC.

Inventor： Martin L. VOOGEL ,  Matthew H. KLEIN

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498

Abstract: Examples herein describe techniques for producing a three-dimensional (3D) die stack. The techniques include stacking a first die on top of a second die. The first die is offset from the second die in at least one of an x-direction and a y-direction, and a first routing sub-region of the first die aligns with a second routing sub-region of the second die. The techniques further include stacking a third die on top of the second die. The third die is offset from the second die in at least one of the x-direction and the y-direction, and a third routing sub-region of the third die aligns with a fourth routing sub-region of the second die.

公开(公告)号：US20240329126A1

公开(公告)日：2024-10-03

申请号：US18128947

申请日：2023-03-30

Applicant: XILINX, INC.

Inventor： Dinesh D. GAITONDE ,  Matthew H. KLEIN ,  Himanshu VERMA ,  Chirag RAVISHANKAR ,  Maithilee Rajendra KULKARNI

IPC: G01R31/28

CPC classification number: G01R31/2896 ,  G01R31/287

Abstract: Embodiments herein describe assigning integrated circuits with defects as variants of the integrated circuit design. Each variant can deactivate different circuitry in the integrated circuit design. A location of the defect can be matched to a variant that has a deactivated region that covers the defect. The integrated circuit can then be assigned to that variant.

公开(公告)号：US20220199604A1

公开(公告)日：2022-06-23

申请号：US17693256

申请日：2022-03-11

Applicant: XILINX, INC.

Inventor： Matthew H. KLEIN

IPC: H01L25/18 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00

Abstract: Some examples described herein provide for a multi-chip structure including one or more memory dies stacked on a die having a programmable integrated circuit (IC). In an example, a multi-chip structure includes a package substrate, a first die, and a second die. The first die includes a programmable IC, and the programmable IC includes a memory controller. The first die is on and attached to the package substrate. The second die includes memory. The second die is stacked on the first die. The memory is communicatively coupled to the memory controller.

公开(公告)号：US20240330557A1

公开(公告)日：2024-10-03

申请号：US18128368

申请日：2023-03-30

Applicant: XILINX, INC.

Inventor： Martin L. VOOGEL ,  Matthew H. KLEIN

IPC: G06F30/392 ,  G06F30/398

CPC classification number: G06F30/392 ,  G06F30/398

Abstract: Embodiments herein describe various 2×2 configuration of integrated circuits (ICs), where the ICs can communicate with multiple neighboring ICs using chip-to-chip interfaces. As such, 2×2 configurations are improvements over other horizontal chip integration formats (such as 1×2, 1×3, and 1×4) where some of the ICs can directly communicate with only one other IC.