公开(公告)号：US20150084680A1

公开(公告)日：2015-03-26

申请号：US14191403

申请日：2014-02-26

申请人： Zhihong Cheng ,  Zhijun Chen ,  Huabin Du ,  Peidong Wang ,  Shayan Zhang

发明人： Zhihong Cheng ,  Zhijun Chen ,  Huabin Du ,  Peidong Wang ,  Shayan Zhang

IPC分类号： H03K17/22

CPC分类号： G11C5/14

摘要： A state retention power gated (SRPG) cell includes a retention circuit coupled to a power gated circuit. The retention circuit stores state information of the power gated circuit before a low power period is started. A gated power supply coupled to the power gated circuit and to a first end of a power supply switch supplies a gated supply voltage to the power gated circuit during a non-low power period. A local power supply coupled to the retention circuit and to a second end of the power supply switch is coupled to the gated power supply in the non-low power period, and a non-gated power supply is coupled to the local power supply via an isolation element to isolate the non-gated power supply from the local power supply during the non-low power period, and to couple the non-gated power supply to the local power supply during the low power period.

摘要翻译： 状态保持功率门控（SRPG）单元包括耦合到电源门控电路的保持电路。 保持电路在开始低功率周期之前存储电源门控电路的状态信息。 耦合到电源门控电路和电源开关的第一端的门控电源在非低功率时段期间向门控电路提供门控电源电压。 耦合到保持电路和电源开关的第二端的局部电源在非低功率时段内耦合到门控电源，并且非门控电源经由 隔离元件，以在非低功率周期期间将非门控电源与本地电源隔离，并且在低功率周期期间将非门控电源耦合到本地电源。

公开(公告)号：US20140096103A1

公开(公告)日：2014-04-03

申请号：US13723207

申请日：2012-12-21

申请人： Peidong Wang ,  Zhijun Chen ,  Zhihong Cheng ,  Li Ying

发明人： Peidong Wang ,  Zhijun Chen ,  Zhihong Cheng ,  Li Ying

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G03F7/70433 ,  G06F2217/12 ,  Y02P90/265

摘要： A system for optimizing the number of dies that can be fabricated on a wafer uses a die number optimization (DNO) routine to determine a maximum number of dies for a target die area (TDA), and generate an initial result list of die shapes that have the maximum number of dies for the TDA. Optionally, a die size optimization (DSO) routine can be executed to determine a list of die shapes having a maximum die area corresponding to the maximum number of dies, a first list of optimized die shapes having a maximum area utilization (AU) for a decreased TDA, and/or a second list of optimized die shapes having a minimum AU for an increased TDA. A candidate list (CL) of the various die shapes can be generated, and entries from the CL automatically selected and/or displayed to indicate proposed wafer layouts.

摘要翻译： 用于优化晶片上可制造的管芯数量的系统使用管芯数量优化（DNO）程序来确定目标管芯区域（TDA）的最大数量的管芯，并且生成模具形状的初始结果列表，其中， 具有TDA的最大数量的模具。 可选地，可以执行管芯尺寸优化（DSO）程序以确定具有与最大数量的管芯相对应的最大管芯面积的管芯形状的列表，具有最大面积利用率（AU）的优化管芯形状的第一列表， 和/或用于增加的TDA具有最小AU的优化模具形状的第二列表。 可以生成各种模具形状的候选列表（CL），并且自动选择和/或显示来自CL的条目以指示所提出的晶片布局。

公开(公告)号：US08671381B1

公开(公告)日：2014-03-11

申请号：US13723207

申请日：2012-12-21

申请人： Peidong Wang ,  Zhijun Chen ,  Zhihong Cheng ,  Li Ying

发明人： Peidong Wang ,  Zhijun Chen ,  Zhihong Cheng ,  Li Ying

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G03F7/70433 ,  G06F2217/12 ,  Y02P90/265

摘要： A system for optimizing the number of dies that can be fabricated on a wafer uses a die number optimization (DNO) routine to determine a maximum number of dies for a target die area (TDA), and generate an initial result list of die shapes that have the maximum number of dies for the TDA. Optionally, a die size optimization (DSO) routine can be executed to determine a list of die shapes having a maximum die area corresponding to the maximum number of dies, a first list of optimized die shapes having a maximum area utilization (AU) for a decreased TDA, and/or a second list of optimized die shapes having a minimum AU for an increased TDA. A candidate list (CL) of the various die shapes can be generated, and entries from the CL automatically selected and/or displayed to indicate proposed wafer layouts.

摘要翻译： 用于优化晶片上可制造的管芯数量的系统使用管芯数量优化（DNO）程序来确定目标管芯区域（TDA）的最大数量的管芯，并且生成模具形状的初始结果列表，其中， 具有TDA的最大数量的模具。 可选地，可以执行管芯尺寸优化（DSO）程序以确定具有与最大数量的管芯相对应的最大管芯面积的管芯形状的列表，具有最大面积利用率（AU）的优化管芯形状的第一列表， 和/或用于增加的TDA具有最小AU的优化模具形状的第二列表。 可以生成各种模具形状的候选列表（CL），并且自动选择和/或显示来自CL的条目以指示所提出的晶片布局。

公开(公告)号：US09191021B1

公开(公告)日：2015-11-17

申请号：US14696482

申请日：2015-04-26

申请人： Zhiling Sui ,  Zhijun Chen ,  Zhihong Cheng ,  Yanping Zhang

发明人： Zhiling Sui ,  Zhijun Chen ,  Zhihong Cheng ,  Yanping Zhang

IPC分类号： H03M1/10 ,  H03M1/12 ,  H03M1/42 ,  H03M1/44

CPC分类号： H03M1/0639 ,  H03M1/0695 ,  H03M1/1009 ,  H03M1/12 ,  H03M1/164 ,  H03M1/44

摘要： A pipelined analog-to-digital converter (ADC) that converts an analog input voltage signal Vin into a digital output value Dout. The ADC has a sequence of stages including a first calibrated stage having: (1) an ADC sub-module that receives Vin and provides an ADC sub-module digital output value based on Vin, (2) a DAC sub-module that receives the ADC sub-module digital output value and outputs a corresponding analog voltage signal VDAC, (3) a first difference module that generates an analog residual-voltage signal based on a difference between Vin and VDAC, and (4) an artificial-noise-insertion module that inserts an analog artificial-noise voltage signal into the residual voltage signal to generate an analog combined voltage signal. The analog combined voltage signal is used to calibrate the first calibrated stage. The artificial-noise-insertion module generates the polarity of the artificial-noise voltage signal based on the polarity of the corresponding residual voltage signal.

摘要翻译： 用于将模拟输入电压信号Vin转换为数字输出值Dout的流水线模数转换器（ADC）。 ADC具有一系列级，包括第一校准级，其具有：（1）ADC子模块，其接收Vin并基于Vin提供ADC子模块数字输出值，（2）DAC子模块，其接收 ADC子模块数字输出值，并输出相应的模拟电压信号VDAC，（3）基于Vin和VDAC之间的差产生模拟残留电压信号的第一差分模块，（4）人造噪声插入 模块，其将模拟人造噪声电压信号插入残余电压信号中以产生模拟组合电压信号。 模拟组合电压信号用于校准第一个校准级。 人造噪声插入模块基于相应的残留电压信号的极性产生人为噪声电压信号的极性。

公开(公告)号：US20130111099A1

公开(公告)日：2013-05-02

申请号：US13604639

申请日：2012-09-06

申请人： Shixiang NIE ,  Zhijun Chen ,  Zhihong Cheng

发明人： Shixiang NIE ,  Zhijun Chen ,  Zhihong Cheng

IPC分类号： G06F13/40

CPC分类号： G06F15/7867

摘要： A processor with programmable virtual ports includes a plurality of in/out (IO) pins for transmitting and receiving data. The IO pins are grouped into a plurality of predefined ports, each of which has a physical address stored in one of a memory location of a memory map. The IO pins may be remapped to one or more virtual ports.

摘要翻译： 具有可编程虚拟端口的处理器包括用于发送和接收数据的多个输入/输出（IO）引脚。 IO引脚被分组成多个预定义端口，每个预定端口具有存储在存储器映射的存储器位置之一中的物理地址。 IO引脚可以被重新映射到一个或多个虚拟端口。

公开(公告)号：US08650327B2

公开(公告)日：2014-02-11

申请号：US13604639

申请日：2012-09-06

申请人： Shixiang Nie ,  Zhijun Chen ,  Zhihong Cheng

发明人： Shixiang Nie ,  Zhijun Chen ,  Zhihong Cheng

IPC分类号： G06F3/00

CPC分类号： G06F15/7867

摘要： A processor with programmable virtual ports includes a plurality of in/out (IO) pins for transmitting and receiving data. The IO pins are grouped into a plurality of predefined ports, each of which has a physical address stored in one of a memory location of a memory map. The IO pins may be remapped to one or more virtual ports.

摘要翻译： 具有可编程虚拟端口的处理器包括用于发送和接收数据的多个输入/输出（IO）引脚。 IO引脚被分组成多个预定义端口，每个预定端口具有存储在存储器映射的存储器位置之一中的物理地址。 IO引脚可以被重新映射到一个或多个虚拟端口。

公开(公告)号：US08569992B2

公开(公告)日：2013-10-29

申请号：US13047801

申请日：2011-03-15

申请人： Zhihong Cheng ,  Zhijun Chen ,  Shixiang Nie

发明人： Zhihong Cheng ,  Zhijun Chen ,  Shixiang Nie

IPC分类号： H02P8/00

CPC分类号： H02P8/12

摘要： A stepper motor controller includes control circuitry with control outputs and individual driver pulse width modulation (PWM) circuitry with individual driver PWM outputs and modulation control inputs coupled to the control outputs. There is a group of individual drivers, each one having an input coupled to one of the PWM outputs, and an output coupled to an individual driver terminal of the controller. There is common driver PWM circuitry having a common driver PWM output. A common driver having a common driver input is coupled to the common driver PWM output and a common driver output is coupled to a common driver terminal of the controller. When a coil is connected between respective driver terminals and the common driver terminal, individual PWM driver currents are supplied to the coils from the individual driver terminals and a common PWM driver current is supplied to the coils from the common driver terminal.

摘要翻译： 步进电机控制器包括具有控制输出的控制电路和具有单独驱动器PWM输出的单独的驱动器脉宽调制（PWM）电路和耦合到控制输出的调制控制输入。 存在一组单独的驱动器，每个驱动器具有耦合到一个PWM输出的输入，以及耦合到控制器的单独驱动器端子的输出。 有普通驱动器PWM电路具有公共驱动器PWM输出。 具有公共驱动器输入的公共驱动器耦合到公共驱动器PWM输出，并且公共驱动器输出耦合到控制器的公共驱动器端子。 当线圈连接在相应的驱动器端子和公共驱动器端子之间时，各个驱动器端子将各个PWM驱动器电流提供给线圈，并且公共的驱动器电流从公共驱动器端子提供给线圈。

公开(公告)号：US08554274B2

公开(公告)日：2013-10-08

申请号：US13334039

申请日：2011-12-21

申请人： Hui Zhao ,  Zhengyue Yan ,  Qi Xiao ,  Zhijun Chen ,  Zheng Li

发明人： Hui Zhao ,  Zhengyue Yan ,  Qi Xiao ,  Zhijun Chen ,  Zheng Li

IPC分类号： H04M1/00

CPC分类号： H04M1/21 ,  G03B29/00 ,  H04M1/0272 ,  H04M2250/54

摘要： The invention provides a cell phone projector including a housing, a circuit device, a power supply, a projector module, wherein the circuit device and the power supply are disposed in the housing, and the projector module is displaced at one end of the housing, and wherein the housing is provided with a fence-type slot for insertion of a cell phone. The cell phone is inserted into the slot to thereby achieve to connect the cell phone with a projector. In use, a video signal within the cell phone can be easily output through the projector, to bring a better visual effect for users, and it is convenient for people to watch the video.

摘要翻译： 本发明提供了一种手机投影仪，其包括壳体，电路装置，电源，投影仪模块，其中电路装置和电源设置在壳体中，并且投影仪模块在壳体的一端移位， 并且其中所述壳体设置有用于插入蜂窝电话的栅栏型槽。 将手机插入插槽中，从而实现将手机与投影仪连接。 在使用中，手机中的视频信号可以通过投影机轻松输出，为用户带来更好的视觉效果，方便人们观看视频。

公开(公告)号：US09225568B1

公开(公告)日：2015-12-29

申请号：US14694927

申请日：2015-04-23

申请人： Wangsheng Mei ,  Zhijun Chen ,  Zhiling Sui ,  Yan Xiao

发明人： Wangsheng Mei ,  Zhijun Chen ,  Zhiling Sui ,  Yan Xiao

IPC分类号： H04L27/14 ,  H04L27/156

CPC分类号： H04L27/1563

摘要： A demodulator suitable for demodulating binary FSK signals having a small difference between carrier frequencies uses a counter-timer technique for timing a fixed number FSK cycles and comparing a count value with a threshold when a frequency change is expected. By grouping a number of FSK pulses (or cycles) together in one measurement, speed requirements on the system clock used for the counter/timer measurements can be relaxed and tolerance to noise is also improved. The demodulator is particularly suitable for wireless charging applications.

摘要翻译： 适用于解调载波频率差小的二进制FSK信号的解调器使用计时器技术来定时固定数量的FSK周期，并且当预期频率变化时将计数值与阈值进行比较。 通过在一次测量中将多个FSK脉冲（或周期）分组在一起，可以放宽用于计数器/定时器测量的系统时钟的速度要求，同时提高对噪声的容限。 解调器特别适用于无线充电应用。