公开(公告)号：US10783295B1

公开(公告)日：2020-09-22

申请号：US16399493

申请日：2019-04-30

Applicant: Xilinx, Inc.

Inventor： Xiao Dong ,  Grigor S. Gasparyan ,  Abhishek Joshi

IPC: G06F30/00 ,  G06F30/327 ,  G06F30/34

Abstract: An example method for compiling includes, by a processor-based system: obtaining a netlist of an application, the netlist containing program nodes and respective edges between the program nodes, the application to be implemented on a device comprising an array of data processing engines; partitioning the netlist into a plurality of partitions; for each of the plurality of partitions: generating a global mapping of the program nodes based on a representation of the array of data processing engines and using an integer linear programming (ILP) algorithm; generating a detailed mapping of the program nodes based on the global mapping; and translating the detailed mapping for each of the plurality of partitions to a file.

公开(公告)号：US10963615B1

公开(公告)日：2021-03-30

申请号：US16399445

申请日：2019-04-30

Applicant: Xilinx, Inc.

Inventor： Abhishek Joshi ,  Grigor S. Gasparyan

IPC: G06F30/394 ,  H03K19/1776 ,  H03K19/17736 ,  G06F30/33 ,  G06F30/327

Abstract: Some examples described herein relate to routing in routing elements. In an example, a design system includes a processor and a memory, storing instruction code, coupled to the processor. The processor is configured to execute the instruction code to model a communication network comprising switches interconnected in an array of data processing engines (DPEs), generate global routes of nets in the modeled communication network, generate detailed routes of the nets using the global routes, and translate the detailed routes to a file. Each of the switches has multiple input or output channels connected to another switch that are modeled as a single input or output edge, respectively, connected to the other switch. Each global route is generated through edge(s) of the switches. Each detailed route is generated comprising identifying one of the multiple input or output channels modeled by each edge through which the respective global route is generated.

公开(公告)号：US10853541B1

公开(公告)日：2020-12-01

申请号：US16399661

申请日：2019-04-30

Applicant: Xilinx, Inc.

Inventor： Abhishek Joshi ,  Grigor S. Gasparyan ,  Aditya Chaubal ,  Sridhar Kirshnamurthy ,  Xiao Dong

IPC: G06F30/327 ,  G06F30/331 ,  G06F30/34 ,  G06F13/40 ,  G06F15/78

Abstract: Some examples described herein relate to global mapping of program nodes of a netlist of an application. In an example, a design system includes a processor and a memory coupled to the processor. The memory stores instruction code. The processor is configured to execute the instruction code to obtain a netlist of an application. The netlist contains program nodes and respective edges between the program nodes. The application is to be implemented on a device comprising an array of data processing engines. The processor is also configured to execute the instruction code to generate a global mapping of the program nodes based on a representation of the array of data processing engines and using an integer linear programming (ILP) algorithm; generate a detailed mapping of the program nodes based on the global mapping; and translate the detailed mapping to a file.

公开(公告)号：US09330220B1

公开(公告)日：2016-05-03

申请号：US14467908

申请日：2014-08-25

Applicant: Xilinx, Inc.

Inventor： Mehrdad E. Dehkordi ,  Marvin Tom ,  Sridhar Krishnamurthy ,  Abhishek Joshi

IPC: G06F17/50 ,  G06F1/10

CPC classification number: G06F17/5072 ,  G06F1/10 ,  G06F17/5027 ,  G06F17/5077 ,  G06F2217/62

Abstract: Clock region partitioning and clock routing includes creating partitions for a plurality of clocks of a circuit design, and legalizing the partitions using a processor according to a number of clocks in each partition and assignment of clock distribution tracks. Roots for implementing clock trees of the clocks are selected within the partitions.

Abstract translation: 时钟区域划分和时钟路由包括为电路设计的多个时钟创建分区，以及根据每个分区中的时钟数量和时钟分配轨道的分配，使用处理器对分区进行合法化。 在分区内选择实现时钟树的根。