公开(公告)号：US10419203B1

公开(公告)日：2019-09-17

申请号：US15444002

申请日：2017-02-27

Applicant: Xilinx, Inc.

Inventor： Paolo Novellini ,  Antonello Di Fresco

IPC: H04L7/033

Abstract: An example circuit includes: a transmitter configured to transmit a clock pattern based on a transmit clock; a receiver, coupled to the transmitter, configured to sample the clock pattern based on a receive clock to generate a bit pattern, where there is a non-zero frequency difference between the transmit clock and the receive clock; a phase interpolator (PI) configured to add a phase shift to a source clock to supply one of the transmit clock or the receive clock; and a test circuit configured to apply adjustments to the phase shift over a time period and determine a phase distribution of the PI based on changes in the bit pattern over the time period.

公开(公告)号：US10348312B1

公开(公告)日：2019-07-09

申请号：US15993508

申请日：2018-05-30

Applicant: Xilinx, Inc.

Inventor： Paolo Novellini ,  Antonello Di Fresco

IPC: H03L7/081 ,  H03L7/08 ,  H03L7/091 ,  H04L1/20 ,  G11C7/22 ,  H04L7/033

Abstract: A circuit for receiving data is described. The circuit comprises a phase detector circuit comprising a detector having a first input configured to receive a sum of an oscillator phase and a phase error, and a second input coupled to an output of a first sample selector; a second sample selector having an input coupled to receive the input data and generate output data; and an eye detection circuit comprising a third sample selector having an input coupled to receive the input data and a comparator for comparing outputs of the second sample selector and the third sample selector to determine how much an eye is open for a plurality of channels. A method of implementing a receiver is also described.