公开(公告)号：US09824173B1

公开(公告)日：2017-11-21

申请号：US14852173

申请日：2015-09-11

Applicant: Xilinx, Inc.

Inventor： Bennet An ,  Henry E. Styles ,  Sonal Santan ,  Fernando J. Martinez Vallina ,  Pradip K. Jha ,  David A. Knol ,  Sudipto Chakraborty ,  Jeffrey M. Fifield ,  Stephen P. Rozum

IPC: G06F17/50

CPC classification number: G06F17/5054

Abstract: A software development-based compilation flow for circuit design may include executing, using a processor, a makefile including a plurality of rules for hardware implementation. Responsive to executing a first rule of the plurality of rules, a source file including a kernel specified in a high level programming language may be selected; and, an intermediate file specifying a register transfer level implementation of the kernel may be generated using the processor. Responsive to executing a second rule of the plurality of rules, a configuration bitstream for a target integrated circuit may be generated from the intermediate file using the processor. The configuration bitstream includes a compute unit circuit implementation of the kernel.