公开(公告)号：US09679092B1

公开(公告)日：2017-06-13

申请号：US14931650

申请日：2015-11-03

Applicant: Xilinx, Inc.

Inventor： Pradip K. Jha ,  Ravi N. Kurlagunda ,  David A. Knol ,  Dinesh K. Monga ,  Stephen P. Rozum ,  Sudipto Chakraborty

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5022 ,  G06F17/5031 ,  G06F17/504 ,  G06F17/505 ,  G06F2217/84

Abstract: Constraint handling for a circuit design may include determining, using a processor, instances of parameterizable modules of a circuit design associated with constraints based upon a predefined hardware description language attribute within the instances, extracting, using the processor, parameter values from the instances of the parameterizable modules, and generating, using the processor, static constraint files for the instances of the parameterizable modules using the extracted parameter values.

公开(公告)号：US09646118B1

公开(公告)日：2017-05-09

申请号：US14493154

申请日：2014-09-22

Applicant: Xilinx, Inc.

Inventor： Rajvinder S. Klair ,  David A. Knol ,  Sudipto Chakraborty

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F17/5045 ,  G06F2217/04

Abstract: Simulators are linked to a circuit design tool by establishing a plurality of simulator objects in response to a plurality of registration commands, respectively. Each registration command specifies a simulation interface application associated with one of the simulators, and the simulation interface application has procedures for initiating functions of the associated simulator. For each simulator, values of properties of the simulator are stored in the respective simulator object. The values of the properties include references to the procedures of the associated simulation interface application. An interface, which is responsive to input commands, accesses the values of the properties and executes the procedures referenced by the values of the properties to initiate the functions of the simulators.

公开(公告)号：US11232219B1

公开(公告)日：2022-01-25

申请号：US16264101

申请日：2019-01-31

Applicant: Xilinx, Inc.

Inventor： Bin Ochotta ,  Alec J. Wong ,  Nghia Do ,  Dennis McCrohan ,  David A. Knol ,  Premduth Vidyanandan ,  Satyam Jani

IPC: G06F21/62 ,  H04L9/08 ,  G06F21/10 ,  G06F21/76 ,  H04L9/32 ,  G06F21/60 ,  H04L9/14 ,  G06F21/64 ,  G06F21/12

Abstract: Removing protections on a session-key protected design include receiving a double encrypted vendor private key and an encrypted session key. The double encrypted vendor private key is decrypted into a single encrypted vendor-private key using a user private key, and the single encrypted vendor-private key is decrypted into a vendor private key using a vendor pass phrase. The encrypted session key is decrypted into a session key using the vendor private key, and the session-key protected design is decrypted into a plain design using the session key.

公开(公告)号：US09465903B1

公开(公告)日：2016-10-11

申请号：US14546684

申请日：2014-11-18

Applicant: Xilinx, Inc.

Inventor： Suman Kumar Timmireddy ,  Heera Nand ,  Awdhesh Kumar Sahu ,  Brendan M. O'Higgins ,  David A. Knol ,  Siddharth Rele

IPC: G06F17/50 ,  G06F19/00 ,  H03K19/177 ,  G06F21/12 ,  G06F15/78

CPC classification number: G06F17/5054 ,  G06F15/7867 ,  G06F17/50 ,  G06F17/5022 ,  G06F21/125 ,  H03K19/17728 ,  H03K19/17748

Abstract: A method of implementing a circuit design in a circuit design tool for configuration in a programmable integrated circuit (IC) connected to components on a circuit board is described. The method includes processing a first file associated with the circuit board to obtain descriptions of circuit board interfaces of the components on the circuit board; displaying a graphic user interface (GUI) of the circuit design tool to connect a circuit board interface described in the first file with a circuit design interface in the circuit design; generating physical constraints on the circuit design interface with respect to input/outputs of the programmable IC described as being connected to the selected circuit board interface; and generating a bitstream to configure the programmable IC. The bitstream includes a physical implementation of the circuit design satisfying the physical constraints.

Abstract translation: 描述了在用于配置在与电路板上的部件连接的可编程集成电路（IC）中的电路设计工具中实现电路设计的方法。 该方法包括处理与电路板相关联的第一文件以获得电路板上组件的电路板接口的描述; 显示所述电路设计工具的图形用户界面（GUI），以将所述第一文件中描述的电路板接口与所述电路设计中的电路设计接口连接; 相对于被描述为连接到所选择的电路板接口的可编程IC的输入/输出，在电路设计接口上产生物理约束; 以及生成比特流以配置可编程IC。 比特流包括满足物理约束的电路设计的物理实现。

公开(公告)号：US08938704B1

公开(公告)日：2015-01-20

申请号：US14444693

申请日：2014-07-28

Applicant: Xilinx, Inc.

Inventor： Siddharth Rele ,  David A. Knol ,  Sumit Nagpal ,  Avdhesh Palliwal ,  Brendan M. O'Higgins

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F17/5081

Abstract: An exemplary method of implementing a circuit design for a programmable integrated circuit (IC) includes, on at least one programmed processor, performing operations including: generating a description of circuit components of the circuit design including first portion of a circuit module that is independent of assignment of resources of the programmable IC; assigning a plurality of the resources of the programmable IC to a plurality of the circuit components including determining at least one resource assignment for the circuit module; and generating a physical implementation of the circuit components for implementation in the programmable IC, including generating a second portion of the circuit module that is dependent on the at least one resource assignment, and combining the second portion of the circuit module with the first portion of the circuit module.

Abstract translation: 实现可编程集成电路（IC）的电路设计的示例性方法包括在至少一个编程的处理器上执行操作，包括：产生电路设计的电路部件的描述，该电路设计包括电路模块的独立于 可编程IC资源的分配; 将多个可编程IC的资源分配给多个电路组件，包括确定电路模块的至少一个资源分配; 以及生成用于在可编程IC中实现的电路部件的物理实现，包括生成依赖于至少一个资源分配的电路模块的第二部分，以及将电路模块的第二部分与 电路模块。

公开(公告)号：US09864828B1

公开(公告)日：2018-01-09

申请号：US14857634

申请日：2015-09-17

Applicant: Xilinx, Inc.

Inventor： Susheel Kumar Puthana ,  Stephen P. Rozum ,  Sudipto Chakraborty ,  David A. Knol ,  Yong Li ,  Fernando J. Martinez Vallina ,  Sonal Santan ,  Nabeel Shirazi ,  Salil R. Raje ,  Ethan T. Parker ,  Suman Kumar Timmireddy ,  Heera Nand

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5072

Abstract: Implementing hardware accelerators using programmable integrated circuits may include performing, using a processor, a design flow on a static circuit design. The static circuit design may specify a region reserved for a hardware accelerator and a static region comprising interface circuitry configured to couple the hardware accelerator with an external node. The design flow may generate an implemented static circuit design. Metadata describing the interface circuitry may be generated using a processor. A device support archive including the implemented static circuit design and the metadata may be written, using the processor, to a computer readable storage medium.

公开(公告)号：US08612916B1

公开(公告)日：2013-12-17

申请号：US13709733

申请日：2012-12-10

Applicant: Xilinx, Inc.

Inventor： Brendan M. O'Higgins ,  Pradip K. Jha ,  Dinesh K. Monga ,  David A. Knol

IPC: G06F17/50

CPC classification number: G06F17/5054

Abstract: A method is provided for exporting design constraints from a circuit design. In response to a first user command indicating a design constraint and a pattern, the design constraint is assigned to each object in the circuit design that matches the pattern, and the pattern is stored in a database. In response to a second user command to export design constraints of the circuit design, for each design constraint assigned to a respective set of objects of the circuit design, a pattern stored in the database that matches the respective set of the objects is determined and the design constraint is added to an export file in a format that uses the determined pattern. Design constraints on individual ones of the set of the objects indicated by the determined pattern are omitted from the export file.

Abstract translation: 提供了一种从电路设计中输出设计约束的方法。 响应于指示设计约束和模式的第一用户命令，将设计约束分配给与模式匹配的电路设计中的每个对象，并且将模式存储在数据库中。 响应于第二用户命令导出电路设计的设计约束，对于分配给电路设计的相应对象集合的每个设计约束，确定存储在数据库中与对象的相应集合匹配的模式，并且 设计约束以使用确定的模式的格式添加到导出文件。 导出文件中省略了由确定的图案指示的对象集中的各个对象的设计约束。

公开(公告)号：US09824173B1

公开(公告)日：2017-11-21

申请号：US14852173

申请日：2015-09-11

Applicant: Xilinx, Inc.

Inventor： Bennet An ,  Henry E. Styles ,  Sonal Santan ,  Fernando J. Martinez Vallina ,  Pradip K. Jha ,  David A. Knol ,  Sudipto Chakraborty ,  Jeffrey M. Fifield ,  Stephen P. Rozum

IPC: G06F17/50

CPC classification number: G06F17/5054

Abstract: A software development-based compilation flow for circuit design may include executing, using a processor, a makefile including a plurality of rules for hardware implementation. Responsive to executing a first rule of the plurality of rules, a source file including a kernel specified in a high level programming language may be selected; and, an intermediate file specifying a register transfer level implementation of the kernel may be generated using the processor. Responsive to executing a second rule of the plurality of rules, a configuration bitstream for a target integrated circuit may be generated from the intermediate file using the processor. The configuration bitstream includes a compute unit circuit implementation of the kernel.

公开(公告)号：US08839166B1

公开(公告)日：2014-09-16

申请号：US13837234

申请日：2013-03-15

Applicant: Xilinx, Inc.

Inventor： Sudipto Chakraborty ,  David A. Knol ,  Stephen P. Rozum ,  Ryan A. Linderman ,  Derrick S. Woods

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F17/505 ,  G06F2217/66

Abstract: A method, non-transitory computer readable medium and apparatus for using an out-of-context sub-block in a hierarchical design flow for an integrated circuit are disclosed. For example, the method identifies one or more sub-blocks in the hierarchical design flow that are eligible for creating the out-of-context sub-block, receives a selection of one of the one or more sub-blocks that are eligible and creates the out-of-context sub-block for the one of the one or more sub-blocks that is selected.

Abstract translation: 公开了一种用于在集成电路的分层设计流程中使用失去上下文子块的方法，非暂时计算机可读介质和装置。 例如，该方法识别分层设计流程中的一个或多个子块，该子块有资格创建失去上下文的子块，接收一个或多个符合条件并创建的子块中的一个的选择 用于所选择的一个或多个子块中的一个的上下文子块。