公开(公告)号：US10810341B1

公开(公告)日：2020-10-20

申请号：US16443244

申请日：2019-06-17

Applicant: Xilinx, Inc.

Inventor： Chirag Ravishankar ,  Davis Moore

IPC: G06F30/30 ,  G06F30/394 ,  G06F111/04

Abstract: Circuit pin constraints input to a design tool specify respective sets of circuit pins belonging to circuit blocks, and input interface pin constraints specify respective sets of interface pins belonging to instances of an interface circuit. The design tool generates pin solutions, and each pin solution includes pin assignments of the circuit pins to the interface pins. The design tool applies an objective function to the pin solutions and selects one pin solution that satisfies the objective function. The design tool then specifies in a circuit design, connections between the circuit pins and the interface pins according to the selected pin solution.

公开(公告)号：US10715149B1

公开(公告)日：2020-07-14

申请号：US16513190

申请日：2019-07-16

Applicant: Xilinx, Inc.

Inventor： Eric F. Dellinger ,  Jay T. Young ,  Brian C. Gaide ,  Chirag Ravishankar ,  Davis Moore ,  Steven P. Young

IPC: H03K19/17736 ,  H03K19/17724

Abstract: A system comprises a pair of configurable logic blocks (CLBs) placed adjacent to each other wherein each of the CLBs includes a plurality of configurable logic elements. A plurality sets of inodes are configured to accept signals to and/or from the CLBs, wherein a first set of inodes is positioned to the left of the adjacent CLBs and a second set of inodes is positioned to the right of the adjacent CLBs. A plurality of bnodes are embedded in the middle of the adjacent CLBs, wherein each bnode is configured to establish a first connection between the bnode and one of the first set of inodes on the left of the CLBs and a second connection between the bnode and one of the second set of inodes on the right of the CLBs. Both the first and second routing connections are localized within the pair of adjacent CLBs.