公开(公告)号：US11824564B1

公开(公告)日：2023-11-21

申请号：US17171608

申请日：2021-02-09

Applicant: Xilinx, Inc.

Inventor： Philip B. James-Roxby ,  Eric F. Dellinger

IPC: H03M7/24 ,  G06F7/483

CPC classification number: H03M7/24 ,  G06F7/483

Abstract: A disclosed compression method includes inputting a data set of floating point values from an input circuit to a compression circuit and detecting non-zero values and sequences of zero values in the data set. The compression circuit outputs, in response to detection of a non-zero value in the data set, the non-zero value to an output circuit. The compression circuit generates, in response to detection of a sequence of zero values in the data set, a subnormal floating point value having significand bits that indicate counted zero values in the sequence, and outputs the subnormal floating point value to the output circuit.

公开(公告)号：US09859896B1

公开(公告)日：2018-01-02

申请号：US14851601

申请日：2015-09-11

Applicant: Xilinx, Inc.

Inventor： Brian C. Gaide ,  Steven P. Young ,  Eric F. Dellinger

IPC: H03K19/177

CPC classification number: H03K19/17744 ,  H03K19/17728

Abstract: In an example, a programmable integrated circuit (IC) includes external contacts configured to interface with a substrate and a plurality of configurable logic elements (CLEs) distributed across a programmable fabric. The programmable IC further includes interconnect circuits disposed between the plurality of CLEs and the external contacts. A plurality of the interconnect circuits is disposed in the plurality of CLEs.

公开(公告)号：US11216275B1

公开(公告)日：2022-01-04

申请号：US16531971

申请日：2019-08-05

Applicant: XILINX, INC.

Inventor： Philip B. James-Roxby ,  Eric F. Dellinger

IPC: G06F9/30 ,  G06F7/499 ,  G06F5/01 ,  G06F7/483 ,  H03M7/24

Abstract: The embodiments herein describe a conversion engine that converts floating point data into integer data using a dynamic scaling factor. To select the scaling factor, the conversion engine compares a default (or initial) scaling factor value to an exponent portion of the floating point value to determine a shift value with which to bit shift a mantissa of the floating point value. After bit shifting the mantissa, the conversion engine determines whether the shift value caused an overflow or an underflow and whether that overflow or underflow violates a predefined policy. If the policy is violated, the conversion engine adjusts the scaling factor and restarts the conversion process. In this manner, the conversion engine can adjust the scaling factor until identifying a scaling factor that converts all the floating point values in the batch without violating the policy.

公开(公告)号：US10715149B1

公开(公告)日：2020-07-14

申请号：US16513190

申请日：2019-07-16

Applicant: Xilinx, Inc.

Inventor： Eric F. Dellinger ,  Jay T. Young ,  Brian C. Gaide ,  Chirag Ravishankar ,  Davis Moore ,  Steven P. Young

IPC: H03K19/17736 ,  H03K19/17724

Abstract: A system comprises a pair of configurable logic blocks (CLBs) placed adjacent to each other wherein each of the CLBs includes a plurality of configurable logic elements. A plurality sets of inodes are configured to accept signals to and/or from the CLBs, wherein a first set of inodes is positioned to the left of the adjacent CLBs and a second set of inodes is positioned to the right of the adjacent CLBs. A plurality of bnodes are embedded in the middle of the adjacent CLBs, wherein each bnode is configured to establish a first connection between the bnode and one of the first set of inodes on the left of the CLBs and a second connection between the bnode and one of the second set of inodes on the right of the CLBs. Both the first and second routing connections are localized within the pair of adjacent CLBs.

公开(公告)号：US10042806B2

公开(公告)日：2018-08-07

申请号：US15013690

申请日：2016-02-02

Applicant: Xilinx, Inc.

Inventor： Alireza S. Kaviani ,  Pongstorn Maidee ,  Eric F. Dellinger

IPC: G06F13/36 ,  G06F13/362 ,  G06F13/00 ,  G06F13/40

Abstract: An example programmable integrated circuit (IC) includes a programmable fabric having a programmable interconnect and wire tracks adjacent to at least one edge of the programmable fabric. The programmable IC further includes at least one ring node integrated with at least one edge of the programmable fabric, the at least one ring node coupled between the programmable interconnect and the wire tracks. The programmable IC further includes a system-in-package (SiP) input/output (IO) circuit coupled to the wire tracks.

公开(公告)号：US20170220508A1

公开(公告)日：2017-08-03

申请号：US15013690

申请日：2016-02-02

Applicant: Xilinx, Inc.

Inventor： Alireza S. Kaviani ,  Pongstorn Maidee ,  Eric F. Dellinger

IPC: G06F13/40 ,  G06F13/362

CPC classification number: G06F13/4068 ,  G06F13/362 ,  G06F13/4022 ,  G06F13/4027

Abstract: An example programmable integrated circuit (IC) includes a programmable fabric having a programmable interconnect and wire tracks adjacent to at least one edge of the programmable fabric. The programmable IC further includes at least one ring node integrated with at least one edge of the programmable fabric, the at least one ring node coupled between the programmable interconnect and the wire tracks. The programmable IC further includes a system-in-package (SiP) input/output (IO) circuit coupled to the wire tracks.