公开(公告)号：US10715149B1

公开(公告)日：2020-07-14

申请号：US16513190

申请日：2019-07-16

Applicant: Xilinx, Inc.

Inventor： Eric F. Dellinger ,  Jay T. Young ,  Brian C. Gaide ,  Chirag Ravishankar ,  Davis Moore ,  Steven P. Young

IPC: H03K19/17736 ,  H03K19/17724

Abstract: A system comprises a pair of configurable logic blocks (CLBs) placed adjacent to each other wherein each of the CLBs includes a plurality of configurable logic elements. A plurality sets of inodes are configured to accept signals to and/or from the CLBs, wherein a first set of inodes is positioned to the left of the adjacent CLBs and a second set of inodes is positioned to the right of the adjacent CLBs. A plurality of bnodes are embedded in the middle of the adjacent CLBs, wherein each bnode is configured to establish a first connection between the bnode and one of the first set of inodes on the left of the CLBs and a second connection between the bnode and one of the second set of inodes on the right of the CLBs. Both the first and second routing connections are localized within the pair of adjacent CLBs.

公开(公告)号：US10467373B2

公开(公告)日：2019-11-05

申请号：US15901761

申请日：2018-02-21

Applicant: Xilinx, Inc.

Inventor： Jay T. Young

IPC: G06F17/50 ,  H01L25/065

Abstract: A method of selecting routing resources in a multi-chip integrated circuit device is described. The method comprises placing a design on the multi-chip integrated circuit device; estimating a number of vias required to enable connections between chips of the multi-chip integrated circuit device that is placed with a portion of the design; identifying an area of a chip having a number of vias that is greater than a maximum number of vias for the area of the chip; selecting a partition window defining resources in the chip that is placed with the portion of the design, where in the partition window is selected to allow the number of vias to meet a maximum requirement of vias for the partition window; and re-placing the portion of the design within the partition window so that the number of vias in the area of the chip is within the maximum number of vias for the area.

公开(公告)号：US20190258767A1

公开(公告)日：2019-08-22

申请号：US15901761

申请日：2018-02-21

Applicant: Xilinx, Inc.

Inventor： Jay T. Young

IPC: G06F17/50 ,  H01L25/065

Abstract: A method of selecting routing resources in a multi-chip integrated circuit device is described. The method comprises placing a design on the multi-chip integrated circuit device; estimating a number of vias required to enable connections between chips of the multi-chip integrated circuit device that is placed with a portion of the design; identifying an area of a chip having a number of vias that is greater than a maximum number of vias for the area of the chip; selecting a partition window defining resources in the chip that is placed with the portion of the design, where in the partition window is selected to allow the number of vias to meet a maximum requirement of vias for the partition window; and re-placing the portion of the design within the partition window so that the number of vias in the area of the chip is within the maximum number of vias for the area.