公开(公告)号：US20190303311A1

公开(公告)日：2019-10-03

申请号：US15944307

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Goran HK Bilski ,  Juan J. Noguera Serra ,  Baris Ozgul ,  Jan Langer ,  Richard L. Walke ,  Ralph D. Wittig ,  Kornelis A. Vissers ,  Philip B. James-Roxby ,  Christopher H. Dick

IPC: G06F13/16 ,  G06F13/40

Abstract: A device may include a plurality of data processing engines. Each data processing engine may include a core and a memory module. Each core may be configured to access the memory module in the same data processing engine and a memory module within at least one other data processing engine of the plurality of data processing engines.

公开(公告)号：US20230131698A1

公开(公告)日：2023-04-27

申请号：US18145810

申请日：2022-12-22

Applicant: Xilinx, Inc.

Inventor： Juan J. Noguera Serra ,  Goran HK Bilski ,  Jan Langer ,  Baris Ozgul ,  Richard L. Walke ,  Ralph D. Wittig ,  Kornelis A. Vissers ,  Tim Tuan ,  David Clarke

IPC: G06F3/06 ,  G06F15/78 ,  G06F15/173

Abstract: A device includes a data processing engine array having a plurality of data processing engines organized in a grid having a plurality of rows and a plurality of columns. Each data processing engine includes a core, a memory module including a memory and a direct memory access engine. Each data processing engine includes a stream switch connected to the core, the direct memory access engine, and the stream switch of one or more adjacent data processing engines. Each memory module includes a first memory interface directly coupled to the core in the same data processing engine and one or more second memory interfaces directly coupled to the core of each of the one or more adjacent data processing engines.

公开(公告)号：US10747531B1

公开(公告)日：2020-08-18

申请号：US15944315

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Jan Langer ,  Baris Ozgul ,  Juan J. Noguera Serra ,  Goran HK Bilski ,  Tim Tuan

IPC: G06F9/302 ,  G06F7/57 ,  G06F15/76 ,  G06F9/30 ,  G06F9/38 ,  G06F7/499 ,  G06F15/80

Abstract: An example core for a data processing engine (DPE) includes a register file, a processor, coupled to the register file. The processor includes a multiply-accumulate (MAC) circuit, and permute circuitry coupled between the register file and the MAC circuit, the permute circuitry configured to concatenate at least one pair of outputs of the register file to provide at least one input to the MAC circuit. The core further includes an instruction decoder, coupled to the processor, configured to decode a very large instruction word (VLIW) to set a plurality of parameters of the processor, the plurality of parameters including first parameters of the permute circuitry and second parameters of the MAC circuit.

公开(公告)号：US20190303033A1

公开(公告)日：2019-10-03

申请号：US15944160

申请日：2018-04-03

Applicant: Xilinx, Inc.

Inventor： Juan J. Noguera Serra ,  Goran HK Bilski ,  Jan Langer ,  Baris Ozgul ,  Tim Tuan ,  Richard L. Walke ,  Ralph D. Wittig ,  Kornelis A. Vissers ,  Christopher H. Dick

IPC: G06F3/06

Abstract: A device may include a plurality of data processing engines. Each of the data processing engines may include a core and a memory module. The plurality of data processing engines may be organized in a plurality of rows. Each core may be configured to communicate with other neighboring data processing engines of the plurality of data processing engines by shared access to the memory modules of the neighboring data processing engines.