公开(公告)号：US11196418B1

公开(公告)日：2021-12-07

申请号：US16842610

申请日：2020-04-07

Applicant: Xilinx, Inc.

Inventor： Samudyatha Suryanarayana ,  Vinit Shah ,  David S. Smith ,  Andrew Tabalujan ,  Arvind R. Bomdica

IPC: H03K19/00 ,  G11C11/4093 ,  H04L25/02

Abstract: Apparatus and associated methods relate to an I/O bank impedance calibration circuit having (a) a replica master resistor coupled to an external precision resistor, and (b) a control circuit configured to calibrate an output impedance of the master resistor to generate a calibrated code to control a replica slave resistor in each bank. In an illustrative example, a signal applied to the replica master resistor may be compared against a programmable reference signal. The control circuit may generate the calibrated code, in response to the comparison result, to calibrate the output impedance of the replica master resistor. By implementing the replica master resistor and the replica slave resistor, impedances of a large number of IOs or banks may be calibrated by the impedance calibration circuit using a single one reference pin.

公开(公告)号：US10530324B1

公开(公告)日：2020-01-07

申请号：US16107117

申请日：2018-08-21

Applicant: Xilinx, Inc.

Inventor： Gubo Huang ,  Xiaobao Wang ,  Andrew Tabalujan ,  Sing-Keng Tan

IPC: H03H7/38 ,  G01R27/14 ,  H01L23/00 ,  H01L25/18 ,  G11C7/10 ,  G11C5/06

Abstract: Examples herein describe a die that includes a testing system (e.g., testing circuitry) for measuring the actual resistance of on-die resistors. When testing the die, an I/O element (e.g., a solder bump) can be used to sweep a voltage across the on-die resistor. The testing system identifies when the voltage across the on-die resistor reaches a predefined reference voltage and measures the corresponding current. Using the measured current and the reference voltage, the testing system can identify the actual resistance of the on-die resistor. In one embodiment, the on-die resistor is tunable such if the on-die resistor has a divergent value, the die can adjust its resistance value to the desired value.

公开(公告)号：US10823780B1

公开(公告)日：2020-11-03

申请号：US16112433

申请日：2018-08-24

Applicant: Xilinx, Inc.

Inventor： Andrew Tabalujan ,  Xiaobao Wang ,  Gubo Huang

IPC: G01R31/28 ,  G01R19/257 ,  H04B17/20 ,  H01L25/065

Abstract: Examples herein describe techniques for testing a receiver interface on a die. In one embodiment, the die includes tester circuitry which includes a digital to analog convertor (DAC) which outputs an analog test signal to a selector circuit (e.g., a multiplexer) which forwards the analog test signal to a receiver. By varying the analog test signal, the tester circuitry can identify one or more trip points corresponding to the receiver. That is, by monitoring the output of the receiver, a testing application can determine when the output of the receiver switches states thereby indicating that the analog test signal at the input of the receiver corresponds to the trip point of the receiver. In this manner, internal circuitry (e.g., the tester circuitry) can be used to test a receiver interface that may otherwise be inaccessible.

公开(公告)号：US10656202B1

公开(公告)日：2020-05-19

申请号：US16137888

申请日：2018-09-21

Applicant: Xilinx, Inc.

Inventor： Sing-Keng Tan ,  Xiaobao Wang ,  Andrew Tabalujan ,  Gubo Huang

IPC: G01R31/317 ,  G01R31/3185

Abstract: Examples of the present disclosure provide example devices that include an integrated circuit that has debugging capability. In some examples, a device includes an integrated circuit die. The integrated circuit die includes an input/output (IO) base cell and a debug port. The IO base cell has an interface node and a feedback node. The interface node is configured to be coupled to memory, such as via an interposer, for communication therebetween. The IO base cell is configurable to selectively output to the feedback node a signal that is on the interface node. The debug port has an input node and an output node. The input node is electrically connected to the feedback node. The debug port is configurable to selectively output to the output node a signal that is on the input node. The output node is configured to be coupled to a pin exterior to the integrated circuit die.