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公开(公告)号：US12026444B2
公开(公告)日：2024-07-02
申请号：US17522834
申请日：2021-11-09
Applicant: Xilinx, Inc.
IPC: G06F30/343 , G06F30/327 , G06F30/347
CPC classification number: G06F30/343 , G06F30/327 , G06F30/347
Abstract: Dynamic port handling for circuit designs can include inserting, within a static isolated module of a circuit design, static drivers configured to drive isolated modules of reconfigurable module (RM) instances for inclusion in an RM of the circuit design. For each RM instance of a plurality of RM instances to be inserted into the RM, one or more additional ports can be inserted in the RM based on a number of isolated modules included in a current RM instance. Further, net(s) corresponding to the additional port(s) can be created. The circuit design, including the current RM instance, the additional port(s), and the net(s), can be placed and routed. Prior to the inserting and the performing place and route for a next RM instance to be inserted into the RM, the current RM instance can be removed from the RM along with the additional port(s) and the net(s).
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公开(公告)号：US10608641B2
公开(公告)日：2020-03-31
申请号：US16041602
申请日：2018-07-20
Applicant: Xilinx, Inc.
Inventor： Hao Yu , Raymond Kong , Brian S. Martin , Jun Liu
IPC: G06F17/50 , G06F15/78 , H03K19/17756 , H03K19/1776 , H03K19/17736 , H03K19/17728 , H03K19/177
Abstract: Hierarchical partial reconfiguration for integrated circuits includes converting, using computer hardware, a first partial reconfiguration module of a circuit design into a first partial reconfiguration container, wherein the circuit design is placed and routed, loading, using the computer hardware, a first netlist into the first partial reconfiguration container, wherein the first netlist includes a first plurality of partial reconfiguration modules that are initially empty, and including, using the computer hardware, a further netlist within each of the first plurality of partial reconfiguration modules. Using the computer hardware, the first partial reconfiguration container is implemented with the first plurality of partial reconfiguration modules being implemented within the first partial reconfiguration container.
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公开(公告)号：US11449347B1
公开(公告)日：2022-09-20
申请号：US16421367
申请日：2019-05-23
Applicant: Xilinx, Inc.
Inventor： Raymond Kong , Brian S. Martin , Hao Yu , Jun Liu , Ashish Sirasao
Abstract: Time-multiplexing implementation of hardware accelerated functions includes associating each function of a plurality of functions from program code with an accelerator binary image specifying a hardware accelerated version of the associated function and determining which accelerator binary images are data independent. Using the computer hardware, the accelerator binary images can be scheduled for implementation in a programmable integrated circuit within each of a plurality of partial reconfiguration regions based on data independence.
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公开(公告)号：US10824786B1
公开(公告)日：2020-11-03
申请号：US15285786
申请日：2016-10-05
Applicant: Xilinx, Inc.
Inventor： Jun Liu , Hao Yu , Raymond Kong , David P. Schultz
IPC: G06F17/50 , G06F30/394 , G06F30/34 , G06F30/327 , G06F30/392 , G06F30/347
Abstract: Method, apparatus and computer-readable medium for providing a partial reconfiguration of a reconfigurable module are described. In one example, a method reads a netlist for a design of a circuit comprising a reconfigurable module and sets the reconfigurable module to a first region. The method then generates a second region that encompasses the first region and places the design with the first region. The method routes the design with the second region and generates a partial bitstream for the reconfigurable module.
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5.发明授权公开(公告)号：US10651853B1
公开(公告)日：2020-05-12
申请号：US16421399
申请日：2019-05-23
Applicant: Xilinx, Inc.
Inventor： Raymond Kong , Hao Yu
IPC: H03K19/17756 , H03K19/17728 , H03K19/17736 , H03K19/1776 , G06F30/34 , G06F30/392 , G06F30/394 , G06F30/3312
Abstract: A device includes a platform implemented in programmable circuitry of the device. The platform is configured to communicate with a host data processing system. The device includes a first partial reconfiguration region implemented in the programmable circuitry and coupled to the platform. The first partial reconfiguration region is reserved for implementing user-specified circuitry. The device includes timing insulation circuitry implemented in the programmable circuitry and configured to isolate timing of signals passing between the platform and the first partial reconfiguration region.
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Patent Agency Ranking
公开(公告)号：US20240202421A1
公开(公告)日：2024-06-20
申请号：US18066852
申请日：2022-12-15
Applicant: Xilinx, Inc.
Inventor： Hao Yu , Raymond Kong
IPC: G06F30/394 , G06F30/398
CPC classification number: G06F30/394 , G06F30/398
Abstract: Bi-directional dynamic function exchange (DFX) can include receiving a circuit design for a programmable integrated circuit (IC). The circuit design includes a plurality of DFX partitions coupled by a signal path. The circuit design can be placed using a first plurality of DFX modules for the plurality of DFX partitions, in part, by selecting a flip-flop of a connection block as a boundary flip-flop of the signal path for each DFX module of the plurality of DFX modules. The circuit design including the signal path can be routed through the selected flip-flops of the connection blocks using a bi-directional routing resource coupling the plurality of connection blocks. The bi-directional routing resource is used as a partition pin placement constraint (PPLOC) node for DFX.
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公开(公告)号：US10558777B1
公开(公告)日：2020-02-11
申请号：US15820926
申请日：2017-11-22
Applicant: Xilinx, Inc.
Inventor： Hao Yu , Raymond Kong
IPC: G06F17/50
Abstract: A method of implementing a partial reconfiguration in an integrated circuit device is described. The method comprises reading a netlist for a design of a circuit comprising a reconfigurable module; defining a first region of the integrated circuit device having the reconfigurable module; defining a second region that encompasses the first region; placing the reconfigurable module of the design in the first region, wherein the reconfigurable module comprises a partition pin of a plurality of available partition pins; selectively removing the partition pin; routing drivers and loads that are in the second region; and generating a partial bitstream for the reconfigurable module.
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公开(公告)号：US20200028511A1
公开(公告)日：2020-01-23
申请号：US16041602
申请日：2018-07-20
Applicant: Xilinx, Inc.
Inventor： Hao Yu , Raymond Kong , Brian S. Martin , Jun Liu
IPC: H03K19/177 , G06F17/50
Abstract: Hierarchical partial reconfiguration for integrated circuits includes converting, using computer hardware, a first partial reconfiguration module of a circuit design into a first partial reconfiguration container, wherein the circuit design is placed and routed, loading, using the computer hardware, a first netlist into the first partial reconfiguration container, wherein the first netlist includes a first plurality of partial reconfiguration modules that are initially empty, and including, using the computer hardware, a further netlist within each of the first plurality of partial reconfiguration modules. Using the computer hardware, the first partial reconfiguration container is implemented with the first plurality of partial reconfiguration modules being implemented within the first partial reconfiguration container.
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公开(公告)号：US10296699B1
公开(公告)日：2019-05-21
申请号：US15468021
申请日：2017-03-23
Applicant: Xilinx, Inc.
Inventor： Hao Yu , Raymond Kong , Jun Liu
IPC: G06F17/50
Abstract: Implementing a circuit design for partial reconfiguration can include routing, using a processor, a net of the circuit design that connects an endpoint within a reconfigurable module with an endpoint within static circuitry external to the reconfigurable module and forming, using the processor, a set of candidate nodes including nodes used to route the net. A node from the set of candidate nodes is determined as the partition pin for partial reconfiguration.
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公开(公告)号：US20230148419A1
公开(公告)日：2023-05-11
申请号：US17522834
申请日：2021-11-09
Applicant: Xilinx, Inc.
IPC: G06F30/343 , G06F30/347 , G06F30/327
CPC classification number: G06F30/343 , G06F30/347 , G06F30/327
Abstract: Dynamic port handling for circuit designs can include inserting, within a static isolated module of a circuit design, static drivers configured to drive isolated modules of reconfigurable module (RM) instances for inclusion in an RM of the circuit design. For each RM instance of a plurality of RM instances to be inserted into the RM, one or more additional ports can be inserted in the RM based on a number of isolated modules included in a current RM instance. Further, net(s) corresponding to the additional port(s) can be created. The circuit design, including the current RM instance, the additional port(s), and the net(s), can be placed and routed. Prior to the inserting and the performing place and route for a next RM instance to be inserted into the RM, the current RM instance can be removed from the RM along with the additional port(s) and the net(s).
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