公开(公告)号：US09209809B1

公开(公告)日：2015-12-08

申请号：US14573815

申请日：2014-12-17

Applicant: Xilinx, Inc.

Inventor： Kevin Geary ,  Ronan Casey ,  Declan Carey ,  Thomas Mallard

IPC: H03K19/094 ,  H03K19/0185 ,  H03K19/003

CPC classification number: H03K19/018514 ,  H03K19/00384

Abstract: A circuit for controlling output swing in a current-mode logic circuit is described. The circuit comprises a plurality of current-mode logic circuits coupled in series; a first current-mode logic circuit of the plurality of current-mode logic circuits coupled to provide a signal to a second current-mode logic circuit of the plurality of current-mode logic circuits; an amplitude detector coupled to detect an amplitude of the signal received at the second current-mode logic circuit; and a control circuit coupled to the amplitude detector; wherein the control circuit generates an amplitude control signal for a current-mode logic circuit of the plurality of current-mode logic circuits based upon a detected amplitude of the signal received at the second current-mode logic circuit. A method of controlling output swing in a current-mode logic circuit is also disclosed.

Abstract translation: 描述用于控制电流模式逻辑电路中的输出摆幅的电路。 电路包括串联耦合的多个电流模式逻辑电路; 所述多个电流模式逻辑电路中的第一电流模式逻辑电路被耦合以向所述多个电流模式逻辑电路中的第二电流模式逻辑电路提供信号; 振幅检测器，被耦合以检测在第二电流模式逻辑电路处接收的信号的幅度; 以及耦合到所述幅度检测器的控制电路; 其中所述控制电路基于在所述第二电流模式逻辑电路处接收的所述信号的检测幅度，生成所述多个电流模式逻辑电路中的电流模式逻辑电路的幅度控制信号。 还公开了一种控制电流模式逻辑电路中的输出摆幅的方法。

公开(公告)号：US10263815B1

公开(公告)日：2019-04-16

申请号：US15837928

申请日：2017-12-11

Applicant: Xilinx, Inc.

Inventor： Kevin Geary ,  Declan Carey ,  Mohamed Elzeftawi

IPC: H04L25/03 ,  H03G3/30 ,  H03K19/177

Abstract: This disclosure relates generally to continuous time linear equalization. In an example of a continuous time linear equalizer, a variable gain circuit includes transistors having gate nodes respectively as a first and a second input node. A first transimpedance circuit is connected between the first input node and a first output node. A second transimpedance circuit is connected between the second input node and a second output node. A source node of each of the first transistor and the second transistor are commonly connected to one another. In the same or another equalizer, output nodes of a first frequency peaking circuit are connected to input nodes of a second frequency peaking circuit. In such a same or another equalizer, an RC feedback circuit has tap-off nodes and summing nodes respectively connected at the output nodes of the first frequency peaking circuit.

公开(公告)号：US09608611B1

公开(公告)日：2017-03-28

申请号：US15009462

申请日：2016-01-28

Applicant: Xilinx, Inc.

Inventor： Catherine Hearne ,  Parag Upadhyaya ,  Kevin Geary

IPC: H03H11/16 ,  H03K5/135 ,  H03K5/00

CPC classification number: H03K5/135 ,  H03K2005/00052 ,  H03K2005/00058

Abstract: A phase interpolator implemented in an integrated circuit to generate a clock signal is described. The phase interpolator comprises a plurality of inputs coupled to receive a plurality of clock signals; a plurality of transistor pairs, each transistor pair having a first transistor coupled to a first output node and a second transistor coupled to a second output node, wherein a first clock signal associated with the transistor pair is coupled to a gate of the first transistor and an inverted first clock signal associated with the transistor pair is coupled to a gate of the second transistor; a first active inductor load coupled to the first output node; and a second active inductor load coupled to the second output node.

公开(公告)号：US11271664B1

公开(公告)日：2022-03-08

申请号：US16513170

申请日：2019-07-16

Applicant: Xilinx, Inc.

Inventor： Frantz Stephane Florent Ngankem Ngankem ,  Kevin Geary

IPC: H04B17/309 ,  H03F3/68 ,  G01R19/00 ,  H03F3/45 ,  H03M1/66 ,  H03K19/17728 ,  H03K19/17756 ,  H03K19/17736 ,  H03K19/1776

Abstract: Apparatus and associated methods relate to generating a programmable differential threshold with a common mode signal derived from a received signal, and comparing a differential component of the received signal to the programmable differential threshold signal to improve signal loss detection accuracy in the presence of noise. In an illustrative example, the comparison may be performed in a signal loss detection circuit. The signal loss detection circuit may, for example, process a received input signal in an independent path in parallel with a main signal path. The programmable differential threshold may be set to a predetermined level as a function of an acceptable noise level. Based on the comparison, some implementations may advantageously respond to received signal loss, which may result from, for example, a signal path interruption.