Method and apparatus for clock phase generation

    公开(公告)号:US09954539B2

    公开(公告)日:2018-04-24

    申请号:US15206634

    申请日:2016-07-11

    Applicant: Xilinx, Inc.

    CPC classification number: H03L7/0891 H03L7/0805 H03L7/0995 H03L7/24 H03M9/00

    Abstract: A method, non-transitory computer readable medium, and circuit for clock phase generation are disclosed. The circuit includes an injection locked oscillator, a loop controller, and a phase interpolator. The injection locked oscillator includes an input for receiving an injected clock signal and an output for forwarding a set of fixed clock phases. The loop controller includes an input for receiving a phase separation error of the fixed clock phases and an output for forwarding a supply voltage derived from the phase separation error. The supply voltage matches the free running frequency of the injection locked oscillator to a frequency of the injected clock signal. The phase interpolator includes an input for receiving the set of fixed clock phases directly from the injection locked oscillator, an input for receiving the supply voltage from the loop controller, and an output for forwarding an arbitrary clock phase.

    Method of implementing a differential integrating phase interpolator

    公开(公告)号:US09876489B1

    公开(公告)日:2018-01-23

    申请号:US15258696

    申请日:2016-09-07

    Applicant: Xilinx, Inc.

    Abstract: The phase interpolator comprises a first charge pump configured to receive a first differential clock signal having a first clock phase, wherein the first charge pump has a first current path and a second current path coupled between a first pull-up current source and a first pull-down current source, wherein the first current path comprises a first NMOS steering switch coupled between a first output node and the first pull-down current source and the second current path comprises a second NMOS steering switch coupled between a second output node and the first pull-down current source; and a second charge pump configured to receive a second differential clock signal having a second clock phase, wherein the second charge pump has a third current path and a fourth current path coupled between a second pull-up current source and a second pull-down current source, and wherein the third current path comprises a third NMOS steering switch coupled between the first output node and the second pull-down current source and the fourth current path comprises a fourth NMOS steering switch coupled between the second node and the second pull-down current source.

    Integrated circuit including a continuous time linear equalizer (CTLE) circuit and method of operation

    公开(公告)号:US11489705B1

    公开(公告)日:2022-11-01

    申请号:US17019035

    申请日:2020-09-11

    Applicant: XILINX, INC.

    Abstract: Some examples described herein provide for an integrated circuit including a continuous time linear equalizer (CTLE) circuit and a method of operating the integrated circuit. In an example, an integrated circuit includes a transconductance amplifier stage and a transimpedance amplifier stage. The transconductance amplifier stage has a first input node and a first output node. The transconductance amplifier stage includes a first complementary device inverter. The transimpedance amplifier stage has a second input node and a second output node. The first output node is electrically connected to the second input node. The transimpedance amplifier stage includes a second complementary device inverter.

    METHOD AND APPARATUS FOR CLOCK PHASE GENERATION

    公开(公告)号:US20180013435A1

    公开(公告)日:2018-01-11

    申请号:US15206634

    申请日:2016-07-11

    Applicant: Xilinx, Inc.

    CPC classification number: H03L7/0891 H03L7/0805 H03L7/0995 H03L7/24 H03M9/00

    Abstract: A method, non-transitory computer readable medium, and circuit for clock phase generation are disclosed. The circuit includes an injection locked oscillator, a loop controller, and a phase interpolator. The injection locked oscillator includes an input for receiving an injected clock signal and an output for forwarding a set of fixed clock phases. The loop controller includes an input for receiving a phase separation error of the fixed clock phases and an output for forwarding a supply voltage derived from the phase separation error. The supply voltage matches the free running frequency of the injection locked oscillator to a frequency of the injected clock signal. The phase interpolator includes an input for receiving the set of fixed clock phases directly from the injection locked oscillator, an input for receiving the supply voltage from the loop controller, and an output for forwarding an arbitrary clock phase.

    Phase interpolator and method of implementing a phase interpolator

    公开(公告)号:US09608611B1

    公开(公告)日:2017-03-28

    申请号:US15009462

    申请日:2016-01-28

    Applicant: Xilinx, Inc.

    CPC classification number: H03K5/135 H03K2005/00052 H03K2005/00058

    Abstract: A phase interpolator implemented in an integrated circuit to generate a clock signal is described. The phase interpolator comprises a plurality of inputs coupled to receive a plurality of clock signals; a plurality of transistor pairs, each transistor pair having a first transistor coupled to a first output node and a second transistor coupled to a second output node, wherein a first clock signal associated with the transistor pair is coupled to a gate of the first transistor and an inverted first clock signal associated with the transistor pair is coupled to a gate of the second transistor; a first active inductor load coupled to the first output node; and a second active inductor load coupled to the second output node.

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