公开(公告)号：US10068048B1

公开(公告)日：2018-09-04

申请号：US15213214

申请日：2016-07-18

Applicant: Xilinx, Inc.

Inventor： Mehrdad Eslami Dehkordi ,  Marvin Tom ,  Sridhar Krishnamurthy ,  Frank Mueller

IPC: G06F17/50

Abstract: The disclosure describes approaches for generating a clock tree for a circuit design. Initial clock trees are generated and elements are assigned to locations on an integrated circuit (IC). Each of the initial clock trees includes a clock root, a spine including the clock root, and branches connected to and extending from the spine. Each clock load is coupled to one of the branches. The clock tree further includes programmable delay circuits having initial delay values that are balanced. If the circuit design does not satisfy timing constraints, at least one clock root is moved from a respective first location to a respective second location.

公开(公告)号：US11709521B1

公开(公告)日：2023-07-25

申请号：US16913716

申请日：2020-06-26

Applicant: Xilinx, Inc.

Inventor： Frederic Revenu ,  Frank Mueller ,  Thomas O. Satter ,  Mehrdad Eslami Dehkordi ,  Garik Mkrtchyan ,  Satish B. Sivaswamy ,  Nicholas A. Mezei ,  Chun Zhang

IPC: G06F1/06

CPC classification number: G06F1/06

Abstract: Synthetizing a hardware description language code into a netlist comprising loads and a multi-clock buffer (MBUF). The MBUF receives a global clocking signal and generates a first and a second related clocking signals. The loads are grouped into a first and a second groups receiving the first and the second clocking signals respectively. A first/second clock modifying leaf are placed between a common node and the first/group groups respectively, wherein the common node is positioned closer in proximity to the first/second groups in comparison to a clock source generating the global clocking signal. The first/second clock modifying leaves receive a least divided clocking signal from the MBUF and generate the first/second clocking signals respectively. The least divided clocking signal is routed from the MBUF to the first/second clock modifying leaves. The first/second clocking signals are routed from the first/second clock modifying leaves to the first/second group respectively.