公开(公告)号：US11429769B1

公开(公告)日：2022-08-30

申请号：US17085838

申请日：2020-10-30

Applicant: Xilinx, Inc.

Inventor： Pradip Kar ,  Nithin Kumar Guggilla ,  Chaithanya Dudha ,  Satyaprakash Pareek

IPC: G06F30/327 ,  G06F30/33 ,  G06F30/398 ,  G11C7/00 ,  G11B5/00 ,  G06F30/343

Abstract: Implementing a hardware description language (HDL) memory includes determining, using computer hardware, a width and a depth of the HDL memory specified as an HDL module for implementation in an integrated circuit (IC), partitioning, using the computer hardware, the HDL memory into a plurality of super slices corresponding to columns and the plurality of super slices into a plurality of super tiles arranged in rows. A heterogeneous memory array may be generated, using the computer hardware. The heterogeneous memory array is formed of different types of memory primitives of the IC. Input and output circuitry configured to access the heterogeneous memory array can be generated using the computer hardware.

公开(公告)号：US20250148179A1

公开(公告)日：2025-05-08

申请号：US18503047

申请日：2023-11-06

Applicant: Xilinx, Inc.

Inventor： Pradip Kar ,  Chaithanya Dudha ,  Nithin Kumar Guggilla

IPC: G06F30/327 ,  G06F30/323

Abstract: A memory includes a read circuit having a first primitive configured to output a first data item based on least significant bits (LSBs) of a read address and a multiplexer coupled to the primitive. The multiplexer outputs a selected bit from the first data item as read data based on most significant bits (MSBs) of the read address. The memory includes a write circuit having a second primitive that outputs a second data item based on LSBs of a write address and a modifier circuit that generates a third data item by modifying a bit of the second data item to correspond to write data. The bit is at a location within the second data item selected based on MSBs of the write address. The modifier circuit writes the third data item to a location in the write primitive based on the LSBs of the write address.

公开(公告)号：US11100267B1

公开(公告)日：2021-08-24

申请号：US16867165

申请日：2020-05-05

Applicant: XILINX, INC.

Inventor： Nithin Kumar Guggilla ,  Pradip Kar ,  Chaithanya Dudha

IPC: G06F30/337

Abstract: Embodiments herein describe techniques for designing a compressed hardware implementation of a user-designed memory. In one example, a user defines a memory in hardware description language (HDL) with a depth (D) and a width (W). To compress the memory, a synthesizer designs a core memory array representing the user-defined memory. Using addresses, the synthesizer can identify groups of nodes in the array that can be compressed into a memory element. The synthesizer designs input circuitry such as a data replicator and a write enable generator for generating the inputs and control signals for the groups. The synthesizer can then implement the design in an integrated circuit where each group of nodes maps to a single memory element, thereby resulting in a compressed design.

公开(公告)号：US11416659B1

公开(公告)日：2022-08-16

申请号：US16834797

申请日：2020-03-30

Applicant: Xilinx, Inc.

Inventor： Pradip Kar ,  Nithin Kumar Guggilla ,  Bing Tian

IPC: G06F30/31 ,  G06F12/02 ,  G06F30/39 ,  G06F30/398 ,  G06F30/392

Abstract: Implementing an asymmetric memory having random port ratios using memory primitives can include detecting, using computer hardware, a hardware description language (HDL) random access memory (RAM) within a circuit design. The HDL RAM is asymmetric. Using computer hardware, a number of a plurality of memory primitives needed to implement the HDL RAM as a RAM circuit are determined based on a maximum port width ratio of the memory primitives defined as 1:N and a port width ratio of the HDL RAM defined as 1:M, wherein each of M and N is an integer and a power of two and M exceeds N. The RAM circuit is asymmetric. Using the computer hardware, a write circuit and/or a read circuit can be generated for a first port of the RAM circuit. Further, using the computer hardware, a write circuit and/or a read circuit can be generated for a second port of the RAM circuit.

公开(公告)号：US10303385B1

公开(公告)日：2019-05-28

申请号：US15451967

申请日：2017-03-07

Applicant: Xilinx, Inc.

Inventor： Michael Keilson ,  Stephen P. Rozum ,  Ryan A. Linderman ,  Pradip Kar

IPC: G06F3/06 ,  G06F17/50 ,  G11C8/16

Abstract: Modifying initialization data for a memory array of a circuit design can include providing, using a processor, portions of an incoming stream of data for initializing the memory array to emulation objects of a memory array emulator. The memory array emulator is configured to emulate an implementation of the memory array and the emulation objects represent block random access memories (block RAMs) of the memory array. Using the processor, the data can be formatted using the emulation objects to generate initialization data, wherein the data is formatted based upon configuration settings of the block RAMs emulated by the respective emulation objects. A configuration bitstream can be updated, using the processor, with the initialization data.