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    AREA OPTIMIZED MEMORY IMPLEMENTATION USING DEDICATED MEMORY PRIMITIVES
    1.
    发明申请
    AREA OPTIMIZED MEMORY IMPLEMENTATION USING DEDICATED MEMORY PRIMITIVES 有权

    公开(公告)号：US20250148179A1

    公开(公告)日：2025-05-08

    申请号：US18503047

    申请日：2023-11-06

    Applicant: Xilinx, Inc.

    Inventor： Pradip Kar ,  Chaithanya Dudha ,  Nithin Kumar Guggilla

    IPC: G06F30/327 ,  G06F30/323

    Abstract: A memory includes a read circuit having a first primitive configured to output a first data item based on least significant bits (LSBs) of a read address and a multiplexer coupled to the primitive. The multiplexer outputs a selected bit from the first data item as read data based on most significant bits (MSBs) of the read address. The memory includes a write circuit having a second primitive that outputs a second data item based on LSBs of a write address and a modifier circuit that generates a third data item by modifying a bit of the second data item to correspond to write data. The bit is at a location within the second data item selected based on MSBs of the write address. The modifier circuit writes the third data item to a location in the write primitive based on the LSBs of the write address.

    Multi dimensional memory compression using bytewide write enable
    2.
    发明授权
    Multi dimensional memory compression using bytewide write enable 有权

    公开(公告)号：US11100267B1

    公开(公告)日：2021-08-24

    申请号：US16867165

    申请日：2020-05-05

    Applicant: XILINX, INC.

    Inventor： Nithin Kumar Guggilla ,  Pradip Kar ,  Chaithanya Dudha

    IPC: G06F30/337

    Abstract: Embodiments herein describe techniques for designing a compressed hardware implementation of a user-designed memory. In one example, a user defines a memory in hardware description language (HDL) with a depth (D) and a width (W). To compress the memory, a synthesizer designs a core memory array representing the user-defined memory. Using addresses, the synthesizer can identify groups of nodes in the array that can be compressed into a memory element. The synthesizer designs input circuitry such as a data replicator and a write enable generator for generating the inputs and control signals for the groups. The synthesizer can then implement the design in an integrated circuit where each group of nodes maps to a single memory element, thereby resulting in a compressed design.

    SMART PREDICTOR CIRCUITRY INSERTION BASED ON STRUCTURAL ANALYSIS AND SWITCHING ACTIVITY
    3.
    发明申请
    SMART PREDICTOR CIRCUITRY INSERTION BASED ON STRUCTURAL ANALYSIS AND SWITCHING ACTIVITY 有权

    公开(公告)号：US20250005249A1

    公开(公告)日：2025-01-02

    申请号：US18344766

    申请日：2023-06-29

    Applicant: Xilinx, Inc.

    Inventor： Fan Zhang ,  Chaithanya Dudha ,  Nithin Kumar Guggilla

    IPC: G06F30/392

    Abstract: Reducing power consumption of a circuit design includes, for a circuit block of a circuit design, where the circuit block has a plurality of signals, selecting one or more signals of the plurality of signals. Prediction and gating circuitry are generated. The prediction and gating circuitry include a predictor circuit configured to generate a prediction of an output of the circuit block based on the one or more signals as selected and gate the circuit block based on the prediction of the output of the circuit block. The prediction and gating circuitry include an output circuit configured to substitute a constant value as the output of the circuit block responsive to gating the circuit block by the predictor circuit. The prediction and gating circuitry are inserted within the circuit design.

    Circuit design transformation for automatic latency reduction
    4.
    发明授权
    Circuit design transformation for automatic latency reduction 有权

    公开(公告)号：US10289786B1

    公开(公告)日：2019-05-14

    申请号：US15634016

    申请日：2017-06-27

    Applicant: Xilinx, Inc.

    Inventor： Chaithanya Dudha ,  Shangzhi Sun ,  Ashish Sirasao ,  Nithin Kumar Guggilla

    IPC: G06F17/50

    Abstract: Reducing latency of a circuit design can include determining, using a processor, a set of sequential circuit elements of a circuit design that meets a condition for removal from the circuit design, wherein the condition is dependent upon a target technology process and a target operating frequency. Using the processor, a feasible cut for a selected sequential circuit element of the set is determined. The selected sequential circuit element and each other sequential circuit element of the set that is part of the cut is removed from the circuit design using the processor.

    RETIMING SEQUENTIAL ELEMENTS HAVING INITITAL STATES
    7.
    发明公开
    RETIMING SEQUENTIAL ELEMENTS HAVING INITITAL STATES 审中-公开

    公开(公告)号：US20240256749A1

    公开(公告)日：2024-08-01

    申请号：US18102490

    申请日：2023-01-27

    Applicant: Xilinx, Inc.

    Inventor： Chaithanya Dudha ,  Ruibing Lu ,  Shangzhi Sun ,  Nithin Kumar Guggilla

    IPC: G06F30/3312 ,  G06F30/392 ,  G06F30/394

    CPC classification number: G06F30/3312 ,  G06F30/392 ,  G06F30/394 ,  G06F2119/12

    Abstract: Retiming a circuit design can include determining whether or not an initial value specified for a candidate register can be removed based on an input logic cone to the candidate register and an output logic cone from the candidate register. The candidate register is a register in a critical path in the circuit design. The candidate register can be retimed into a retimed register in response to determining that the initial value specified for the candidate register can be removed. A new initial value for the retimed register can be derived based on initial values of registers in a logic cone of the retimed register, and the new initial value can be assigned to the retimed register.

    Implementing an asymmetric memory with random port ratios using dedicated memory primitives
    8.
    发明授权
    Implementing an asymmetric memory with random port ratios using dedicated memory primitives 有权

    公开(公告)号：US11416659B1

    公开(公告)日：2022-08-16

    申请号：US16834797

    申请日：2020-03-30

    Applicant: Xilinx, Inc.

    Inventor： Pradip Kar ,  Nithin Kumar Guggilla ,  Bing Tian

    IPC: G06F30/31 ,  G06F12/02 ,  G06F30/39 ,  G06F30/398 ,  G06F30/392

    Abstract: Implementing an asymmetric memory having random port ratios using memory primitives can include detecting, using computer hardware, a hardware description language (HDL) random access memory (RAM) within a circuit design. The HDL RAM is asymmetric. Using computer hardware, a number of a plurality of memory primitives needed to implement the HDL RAM as a RAM circuit are determined based on a maximum port width ratio of the memory primitives defined as 1:N and a port width ratio of the HDL RAM defined as 1:M, wherein each of M and N is an integer and a power of two and M exceeds N. The RAM circuit is asymmetric. Using the computer hardware, a write circuit and/or a read circuit can be generated for a first port of the RAM circuit. Further, using the computer hardware, a write circuit and/or a read circuit can be generated for a second port of the RAM circuit.

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