公开(公告)号：US10802995B2

公开(公告)日：2020-10-13

申请号：US16046602

申请日：2018-07-26

Applicant: Xilinx, Inc.

Inventor： Sarabjeet Singh ,  Hem C. Neema ,  Sonal Santan ,  Khang K. Dao ,  Kyle Corbett ,  Yi Wang ,  Christopher J. Case

IPC: G06F9/38 ,  G06F13/16 ,  G06F9/46 ,  G06F12/0873 ,  G06F12/1045 ,  G06F12/1081

Abstract: A system may include a host processor coupled to a communication bus, a first hardware accelerator communicatively linked to the host processor through the communication bus, and a second hardware accelerator communicatively linked to the host processor through the communication bus. The first hardware accelerator and the second hardware accelerator are directly coupled through an accelerator link independent of the communication bus. The host processor is configured to initiate a data transfer between the first hardware accelerator and the second hardware accelerator directly through the accelerator link.

公开(公告)号：US20200081850A1

公开(公告)日：2020-03-12

申请号：US16046602

申请日：2018-07-26

Applicant: Xilinx, Inc.

Inventor： Sarabjeet Singh ,  Hem C. Neema ,  Sonal Santan ,  Khang K. Dao ,  Kyle Corbett ,  Yi Wang ,  Christopher J. Case

IPC: G06F13/16 ,  G06F12/1045 ,  G06F12/0873 ,  G06F12/1081 ,  G06F9/46

Abstract: A system may include a host processor coupled to a communication bus, a first hardware accelerator communicatively linked to the host processor through the communication bus, and a second hardware accelerator communicatively linked to the host processor through the communication bus. The first hardware accelerator and the second hardware accelerator are directly coupled through an accelerator link independent of the communication bus. The host processor is configured to initiate a data transfer between the first hardware accelerator and the second hardware accelerator directly through the accelerator link.