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    CURRENT LEAKAGE MANAGEMENT CONTROLLER FOR READING FROM MEMORY CELLS
    2.
    发明申请
    CURRENT LEAKAGE MANAGEMENT CONTROLLER FOR READING FROM MEMORY CELLS 有权

    公开(公告)号：US20230023614A1

    公开(公告)日：2023-01-26

    申请号：US17385313

    申请日：2021-07-26

    Applicant: Xilinx, Inc.

    Inventor： Michael Tsivyan ,  Shidong Zhou ,  Karthy Rajasekharan ,  Weiguang Lu ,  Jing Jing Chen ,  Mehul Vashi

    IPC: G11C11/419 ,  G11C11/418 ,  H01L27/11

    Abstract: First and second sensing circuits are coupled to first and second data lines, respectively, and sense levels of current leakage or a memory cell state on the first and second data lines. First and second keeper circuits are coupled to the first and second data lines, respectively, and drive the first and second data lines by a voltage supply through biased transistors. First and second leakage latches are coupled to receive and latch state of signals output from the first and second sensing circuits, respectively. A control circuit is coupled to the first leakage latch, second leakage latch, and outputs of the first and second sensing circuits. The control circuit is configured to select either the signal output from the first sensing circuit or the signal output from the second sensing circuit in response to states of the first and second leakage latches.

    Selectively disconnecting a memory cell from a power supply
    4.
    发明授权
    Selectively disconnecting a memory cell from a power supply 有权

    公开(公告)号：US10566050B1

    公开(公告)日：2020-02-18

    申请号：US15927797

    申请日：2018-03-21

    Applicant: Xilinx, Inc.

    Inventor： Shidong Zhou ,  Nui Chong ,  Jing Jing Chen

    IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412 ,  G11C11/418

    Abstract: Embodiments herein describe a memory cell (e.g., a SRAM memory cell) that includes power selection logic for disconnecting storage inverters from a reference voltage source when writing data into the cell. In one embodiment, the memory cells may be disposed long distances (e.g., more than 100 microns) from the data drivers in the integrated circuit which can result in the data lines having large RC time constants. In one embodiment, disconnecting the memory cells from a power supply may counter (or mitigate) the large RC time constants of the data lines.

    Glitch detector and test glitch generator
    5.
    发明授权
    Glitch detector and test glitch generator 有权

    公开(公告)号：US10466275B1

    公开(公告)日：2019-11-05

    申请号：US16022403

    申请日：2018-06-28

    Applicant: Xilinx, Inc.

    Inventor： Sandeep Vundavalli ,  Sree RKC Saraswatula ,  James D. Wesselkamper ,  Santosh Yachareni ,  Shidong Zhou ,  Anil Kumar Kandala

    IPC: G11C29/00 ,  G01R11/24 ,  G01R31/30 ,  G06F21/86 ,  G06F21/76 ,  G01R22/06

    Abstract: Apparatus and associated methods relate to a glitch detection circuit monitoring a duration that a selected fractional supply voltage is below a predetermined voltage threshold. The selected fractional supply voltage may be at the predetermined threshold when the supply voltage is between a valid circuit-supply voltage and a power-on circuit-reset (POR). A glitch detect signal may be generated, for example, when the monitored duration is greater than a predetermined duration threshold. A test glitch generator may generate a test glitch, for example, having selectable voltage and duration, which may be selectably applied to the glitch detection circuit to verify operation. Various exemplary glitch detection circuits may advantageously determine externally produced tampering attempts by detecting circuit-supply voltages and durations that meet specific selectable supply voltage and duration criteria, improving security of sensitive field programmable gate array (FPGA) data by taking protective action in response to the detection.

    Power on-reset with built-in hysteresis
    6.
    发明授权
    Power on-reset with built-in hysteresis 有权
    内置迟滞电源上电复位

    公开(公告)号：US09407254B1

    公开(公告)日：2016-08-02

    申请号：US14515115

    申请日：2014-10-15

    Applicant: Xilinx, Inc.

    Inventor： Koushik De ,  Santosh Yachareni ,  Shidong Zhou

    IPC: H03L7/00 ,  H03K17/22 ,  H03K3/012 ,  H03K3/037 ,  G06F1/24

    CPC classification number: H03K17/223 ,  G06F1/24 ,  H03K3/0375 ,  H03K5/2472 ,  H03K17/22

    Abstract: A device for controlling a power-on reset signal can include a constant current source, for controlling a reference current that is independent of a supply voltage, and a trip point detector circuit driven by the reference current. The trip point detector circuit detects when the supply voltage of the device exceeds a first trip point voltage, and de-asserts the power-on reset signal when the supply voltage exceeds the first trip point voltage. The first trip point voltage can be controlled by a sum of a threshold voltage of a first n-type metal-oxide-semiconductor transistor, a voltage drop across a first resistor, and a threshold voltage of a first p-type metal-oxide-semiconductor transistor. The device may further include a hysteresis circuit, for detecting when the supply voltage falls below a second trip point voltage and causing the trip point detector circuit to reassert the power-on reset signal.

    Abstract translation: 用于控制上电复位信号的装置可以包括用于控制独立于电源电压的参考电流的恒定电流源和由参考电流驱动的跳变点检测器电路。 跳闸点检测器电路检测器件的电源电压何时超过第一跳变点电压，并且当电源电压超过第一跳变点电压时，去激活上电复位信号。 可以通过第一n型金属氧化物半导体晶体管的阈值电压，跨越第一电阻器的电压降和第一p型金属氧化物半导体晶体管的阈值电压的和来控制第一跳变点电压， 半导体晶体管。 该装置还可以包括滞后电路，用于检测电源电压何时降低到第二跳变点电压以下，并使跳闸点检测器电路重新接通上电复位信号。

    Low offset and enhanced write margin for stacked fabric dies
    7.
    发明授权
    Low offset and enhanced write margin for stacked fabric dies 有权

    公开(公告)号：US11043263B1

    公开(公告)日：2021-06-22

    申请号：US16683846

    申请日：2019-11-14

    Applicant: Xilinx, Inc.

    Inventor： Sree R K C Saraswatula ,  Abhimanyu Kumar ,  Santosh Yachareni ,  Shidong Zhou

    IPC: G11C7/00 ,  G11C11/419 ,  G11C7/10 ,  G11C11/412

    Abstract: A device includes an amplifier, a plurality of selector circuitries, and a plurality of fabric dies. The amplifier is configured to output a supply power signal. Each selector circuitry of the plurality of selector circuitries receives the supply power signal from the amplifier. Each fabric die of the plurality of fabric dies has a corresponding selector circuitry of the plurality of selector circuitries. Each selector circuitry corresponding to a die of the plurality of dies is configured to provide the supply power signal received from the amplifier to its corresponding die responsive to a selection signal being asserted. Selector circuitries of the plurality of selector circuitries corresponding to unselected dies of the plurality of dies pull address supply power for the unselected dies to an input other than the supply power signal of the selector circuitries corresponding to the unselected die.

    Current leakage management controller for reading from memory cells
    10.
    发明授权
    Current leakage management controller for reading from memory cells 有权

    公开(公告)号：US12148464B2

    公开(公告)日：2024-11-19

    申请号：US17385313

    申请日：2021-07-26

    Applicant: Xilinx, Inc.

    Inventor： Michael Tsivyan ,  Shidong Zhou ,  Karthy Rajasekharan ,  Weiguang Lu ,  Jing Jing Chen ,  Mehul Vashi

    IPC: G11C11/419 ,  G11C11/418 ,  H10B10/00

    Abstract: First and second sensing circuits are coupled to first and second data lines, respectively, and sense levels of current leakage or a memory cell state on the first and second data lines. First and second keeper circuits are coupled to the first and second data lines, respectively, and drive the first and second data lines by a voltage supply through biased transistors. First and second leakage latches are coupled to receive and latch state of signals output from the first and second sensing circuits, respectively. A control circuit is coupled to the first leakage latch, second leakage latch, and outputs of the first and second sensing circuits. The control circuit is configured to select either the signal output from the first sensing circuit or the signal output from the second sensing circuit in response to states of the first and second leakage latches.

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