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公开(公告)号：US10177794B1
公开(公告)日：2019-01-08
申请号：US15372221
申请日：2016-12-07
Applicant: Xilinx, Inc.
Inventor： Kumar Rahul , Amarnath Perla , Santosh Yachareni
Abstract: An integrated circuit (IC) includes an encoder configured to receive input data including a plurality of data bits. The encoder includes a parity computation matrix circuit configured to arrange the data bits according to a matrix format to generate a parity computation matrix. A parity computation circuit is configured to compute a plurality of parity computation row terms corresponding to rows of the parity computation matrix respectively, compute a plurality of parity computation column terms corresponding to columns of the parity computation matrix respectively, and compute parity bits using the parity computation row terms and parity computation column terms. Write data including the data bits and the parity bits are provided to a write circuit. The write circuit writes the write data to a memory cell array in a memory.
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公开(公告)号：US12212337B2
公开(公告)日：2025-01-28
申请号：US18128943
申请日：2023-03-30
Applicant: XILINX, INC. , Advanced Micro Devices, Inc.
Inventor： Kumar Rahul , John J. Wuu , Santosh Yachareni
Abstract: An integrated circuit (IC) device includes an error correction code (ECC) encoder circuitry configured to receive input data, determine min-terms in a Hamming matrix (H-Matrix) corresponding to the input data, and generate ECC data based on the min-terms and an output codeword based on the ECC data, and an error correction circuitry configured to generate a corrected output codeword based on the output codeword.
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公开(公告)号：US10886921B1
公开(公告)日：2021-01-05
申请号：US16825340
申请日：2020-03-20
Applicant: XILINX, INC.
Inventor： Vijay Kumar Koganti , Anil Kumar Kandala , Santosh Yachareni
IPC: G06F7/38 , H03K19/177 , H03K19/173 , H01L25/065 , H01L23/00 , H01L25/00 , H03K19/20
Abstract: Examples described herein generally relate to multi-chip devices having stacked chips. In an example, a multi-chip device includes a chip stack including a base chip and two or more overlying chips overlying the base chip. Neighboring chips of the chip stack are connected to each other. The chip stack includes identification generation connections and circuits configured to generate a unique identification of each overlying chip based on a relative position of the respective overlying chip with reference to the base chip. The chip stack includes a communication channel from the base chip to each overlying chip. Each overlying chip includes comparison and enable/disable logic (CEDL) communicatively coupled to the communication channel. The CEDL is configured to compare a target identification of data received by the respective overlying chip to the unique identification of the respective overlying chip and responsively enable or disable a recipient circuit of the respective overlying chip.
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公开(公告)号：US10725841B1
公开(公告)日：2020-07-28
申请号：US15844919
申请日：2017-12-18
Applicant: Xilinx, Inc.
Inventor： Kumar Rahul , Santosh Yachareni
Abstract: An integrated circuit (IC) includes an encoder circuit configured to receive input data including a plurality of data bits. A plurality of parity computation equations for a single error correct double error detect adjacent double error correct adjacent triple error detect (SECDEDADECADTED) Hamming code is received. A plurality of parity bits are computed using the plurality of parity computation equations. Write data including the data bits and the parity bits are provided to a write circuit. The write circuit writes the write data to a memory.
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公开(公告)号：US10466275B1
公开(公告)日：2019-11-05
申请号：US16022403
申请日：2018-06-28
Applicant: Xilinx, Inc.
Inventor： Sandeep Vundavalli , Sree RKC Saraswatula , James D. Wesselkamper , Santosh Yachareni , Shidong Zhou , Anil Kumar Kandala
Abstract: Apparatus and associated methods relate to a glitch detection circuit monitoring a duration that a selected fractional supply voltage is below a predetermined voltage threshold. The selected fractional supply voltage may be at the predetermined threshold when the supply voltage is between a valid circuit-supply voltage and a power-on circuit-reset (POR). A glitch detect signal may be generated, for example, when the monitored duration is greater than a predetermined duration threshold. A test glitch generator may generate a test glitch, for example, having selectable voltage and duration, which may be selectably applied to the glitch detection circuit to verify operation. Various exemplary glitch detection circuits may advantageously determine externally produced tampering attempts by detecting circuit-supply voltages and durations that meet specific selectable supply voltage and duration criteria, improving security of sensitive field programmable gate array (FPGA) data by taking protective action in response to the detection.
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Patent Agency Ranking
公开(公告)号：US10069487B1
公开(公告)日：2018-09-04
申请号：US15463824
申请日：2017-03-20
Applicant: Xilinx, Inc.
Inventor： Anil Kumar Kandala , Santosh Yachareni , Sandeep Vundavalli , Vijay Kumar Koganti , Golla V S R K Prasad , Udaya Kumar Bobbili
IPC: H03H11/26 , H03K3/3565 , H03K19/173 , H03K19/177
Abstract: A disclosed delay circuit includes a plurality of Schmitt triggers that are serially coupled. A first Schmitt trigger of the plurality of Schmitt triggers is configured to receive an input signal. An output control circuit is coupled to receive output signals of two or more Schmitt triggers of the plurality of Schmitt triggers, the output control circuit configured to select a signal from one of the one or more Schmitt triggers as an output signal. The output signal is a delayed version of the input signal.
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公开(公告)号：US09407254B1
公开(公告)日：2016-08-02
申请号：US14515115
申请日：2014-10-15
Applicant: Xilinx, Inc.
Inventor： Koushik De , Santosh Yachareni , Shidong Zhou
CPC classification number: H03K17/223 , G06F1/24 , H03K3/0375 , H03K5/2472 , H03K17/22
Abstract: A device for controlling a power-on reset signal can include a constant current source, for controlling a reference current that is independent of a supply voltage, and a trip point detector circuit driven by the reference current. The trip point detector circuit detects when the supply voltage of the device exceeds a first trip point voltage, and de-asserts the power-on reset signal when the supply voltage exceeds the first trip point voltage. The first trip point voltage can be controlled by a sum of a threshold voltage of a first n-type metal-oxide-semiconductor transistor, a voltage drop across a first resistor, and a threshold voltage of a first p-type metal-oxide-semiconductor transistor. The device may further include a hysteresis circuit, for detecting when the supply voltage falls below a second trip point voltage and causing the trip point detector circuit to reassert the power-on reset signal.
Abstract translation: 用于控制上电复位信号的装置可以包括用于控制独立于电源电压的参考电流的恒定电流源和由参考电流驱动的跳变点检测器电路。 跳闸点检测器电路检测器件的电源电压何时超过第一跳变点电压，并且当电源电压超过第一跳变点电压时，去激活上电复位信号。 可以通过第一n型金属氧化物半导体晶体管的阈值电压，跨越第一电阻器的电压降和第一p型金属氧化物半导体晶体管的阈值电压的和来控制第一跳变点电压， 半导体晶体管。 该装置还可以包括滞后电路，用于检测电源电压何时降低到第二跳变点电压以下，并使跳闸点检测器电路重新接通上电复位信号。
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公开(公告)号：US11662378B2
公开(公告)日：2023-05-30
申请号：US17401875
申请日：2021-08-13
Applicant: XILINX, INC.
CPC classification number: G01R31/3004 , G01R11/24 , G01R22/066 , G06F21/76
Abstract: Detection circuitry for an integrated circuit (IC) includes voltage divider circuitry, comparison circuitry, and calibration circuitry. The voltage divider circuitry receives a power supply signal and output a first reference voltage signal and a supply voltage signal based on the power supply signal. The comparison circuitry compares the first reference voltage signal and the supply voltage signal to generate an output signal. The calibration circuitry alters one or more parameters of the voltage divider circuitry to increase a voltage value of the supply voltage signal based on the comparison of the first reference voltage signal with the supply voltage signal.
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公开(公告)号：US10979034B1
公开(公告)日：2021-04-13
申请号：US16012557
申请日：2018-06-19
Applicant: Xilinx, Inc.
Inventor： Kumar Rahul , Santosh Yachareni , Jitendra Kumar Yadav , Md Nadeem Iqbal , Teja Masina , Sourabh Swarnkar , Suresh Babu Kotha
IPC: H03K3/3562 , H03K3/012 , H03K3/037 , H03K19/0185 , H03K19/00
Abstract: A circuit includes a master latch circuit and a slave latch circuit. The master latch circuit is configured to receive an input data signal associated with an input data voltage domain and generate a first output data signal associated with an output data voltage domain different from the input data voltage domain. The slave latch circuit is configured to receive, from the master latch circuit, the first output data signal and generate a second output data associated with the output data voltage domain.
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公开(公告)号：US10673464B1
公开(公告)日：2020-06-02
申请号：US16106725
申请日：2018-08-21
Applicant: Xilinx, Inc.
Inventor： Kumar Rahul , Santosh Yachareni
Abstract: An apparatus includes an encoder circuit block configured to receive input data. The encoder circuit block is configured to generate a plurality of parity bits from the input data and order the input data and the plurality of parity bits to generate encoded data. The encoder circuit block is configured to generate each of the plurality of parity bits based upon selected bits of the input data and orders the input data and the plurality of parity bits so that a decoder circuit block configured to decode the encoded data is able to perform operations including, at least in part, detecting a no bit error, detecting and correcting a single bit error, detecting a double bit error, detecting and correcting an adjacent double bit error, and detecting an adjacent triple bit error. The operations are independent of a number of memory banks used to store the encoded data. The decoder circuit block may also correct an adjacent triple bit error.
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