公开(公告)号：US11709521B1

公开(公告)日：2023-07-25

申请号：US16913716

申请日：2020-06-26

Applicant: Xilinx, Inc.

Inventor： Frederic Revenu ,  Frank Mueller ,  Thomas O. Satter ,  Mehrdad Eslami Dehkordi ,  Garik Mkrtchyan ,  Satish B. Sivaswamy ,  Nicholas A. Mezei ,  Chun Zhang

IPC: G06F1/06

CPC classification number: G06F1/06

Abstract: Synthetizing a hardware description language code into a netlist comprising loads and a multi-clock buffer (MBUF). The MBUF receives a global clocking signal and generates a first and a second related clocking signals. The loads are grouped into a first and a second groups receiving the first and the second clocking signals respectively. A first/second clock modifying leaf are placed between a common node and the first/group groups respectively, wherein the common node is positioned closer in proximity to the first/second groups in comparison to a clock source generating the global clocking signal. The first/second clock modifying leaves receive a least divided clocking signal from the MBUF and generate the first/second clocking signals respectively. The least divided clocking signal is routed from the MBUF to the first/second clock modifying leaves. The first/second clocking signals are routed from the first/second clock modifying leaves to the first/second group respectively.