公开(公告)号：US20250077760A1

公开(公告)日：2025-03-06

申请号：US18461992

申请日：2023-09-06

Applicant: Xilinx, Inc.

Inventor： Sandip Maity ,  Chun Zhang ,  Aman Gayasen

IPC: G06F30/398

Abstract: Control set optimization for a circuit design includes generating, by a processor, Observability Don't Care (ODC) expressions for registers of the circuit design. Redundant reset pins of the registers of the circuit design are determined by the processor by iteratively checking, on a per-cube and a per-literal basis for each ODC expression, whether a value of a literal causes the ODC expression to evaluate to 1. A modified version of the circuit design is generated by the processor by connecting one or more reset pins of the set of redundant reset pins to one or more constants.

公开(公告)号：US20240330558A1

公开(公告)日：2024-10-03

申请号：US18193197

申请日：2023-03-30

Applicant: Xilinx, Inc.

Inventor： Jichun Wang ,  Wuxi Li ,  Chun Zhang ,  Paul Kundarewich ,  John Blaine

IPC: G06F30/392

CPC classification number: G06F30/392

Abstract: Implementing circuit designs in integrated circuit devices includes determining, using computer hardware, regular control sets, super control sets, and mega control sets for a circuit design. Control set optimization is performed on the circuit design. Performing control set optimization includes performing a clock-enable-only control set reduction for each super control set. Performing control set optimization includes performing a set/reset control set reduction and a clock-enable control set reduction for each mega control set. The circuit design is selectively modified by committing changes determined from the control set reductions to the circuit design on a per control set basis based on an improvement of a cost metric for each control set.

公开(公告)号：US10366001B1

公开(公告)日：2019-07-30

申请号：US15706255

申请日：2017-09-15

Applicant: Xilinx, Inc.

Inventor： Nithin Kumar Guggilla ,  Chaithanya Dudha ,  Krishna Garlapati ,  Chun Zhang ,  Fan Zhang ,  Anup Kumar Sultania

IPC: G06F12/00 ,  G06F12/02 ,  G06F1/3287 ,  G06F13/00 ,  G06F13/28

Abstract: Disclosed approaches of processing a circuit design include determining a subset of addresses of a first RAM of the circuit design that are accessed more often than a frequency threshold. A specification of a second RAM is created for the subset of addresses. A decoder circuit is added to the circuit design. The decoder circuit is configured to enable the second RAM and disable the first RAM in response to an input address in the subset of addresses, and to enable the first RAM and disable the second RAM in response to an input address other than addresses in the subset of addresses.

公开(公告)号：US11709521B1

公开(公告)日：2023-07-25

申请号：US16913716

申请日：2020-06-26

Applicant: Xilinx, Inc.

Inventor： Frederic Revenu ,  Frank Mueller ,  Thomas O. Satter ,  Mehrdad Eslami Dehkordi ,  Garik Mkrtchyan ,  Satish B. Sivaswamy ,  Nicholas A. Mezei ,  Chun Zhang

IPC: G06F1/06

CPC classification number: G06F1/06

Abstract: Synthetizing a hardware description language code into a netlist comprising loads and a multi-clock buffer (MBUF). The MBUF receives a global clocking signal and generates a first and a second related clocking signals. The loads are grouped into a first and a second groups receiving the first and the second clocking signals respectively. A first/second clock modifying leaf are placed between a common node and the first/group groups respectively, wherein the common node is positioned closer in proximity to the first/second groups in comparison to a clock source generating the global clocking signal. The first/second clock modifying leaves receive a least divided clocking signal from the MBUF and generate the first/second clocking signals respectively. The least divided clocking signal is routed from the MBUF to the first/second clock modifying leaves. The first/second clocking signals are routed from the first/second clock modifying leaves to the first/second group respectively.

公开(公告)号：US10943043B1

公开(公告)日：2021-03-09

申请号：US16831229

申请日：2020-03-26

Applicant: XILINX, INC.

Inventor： Jichun Wang ,  Chun Zhang ,  Fan Zhang ,  Bing Tian

IPC: G06F30/30 ,  G06F30/34 ,  G06F30/327 ,  G06F30/337 ,  G06F30/343 ,  G06F30/323

Abstract: Examples described herein provide a method for optimizing a netlist for an integrated circuit device. The method generally includes receiving a netlist comprising a first lookup table, and upstream logic, wherein the upstream logic receives a plurality of input signals and comprises at least one output connected as at least one input to the first lookup table, wherein the first lookup table comprises an unused input and multiple outputs; mapping the plurality of input signals directly to the at least one input and the unused input of the first lookup table; validating the mapping by monitoring the multiple outputs of the first lookup table; and upon a successful validation, optimizing the netlist by removing the upstream logic and reconnecting the plurality of input signals to the at least one input and the unused input of the first lookup table.