公开(公告)号：US11127718B2

公开(公告)日：2021-09-21

申请号：US16741319

申请日：2020-01-13

Applicant: XILINX, INC.

Inventor： Anil Kumar Kandala ,  Vijay Kumar Koganti ,  Santosh Yachareni

IPC: H01L21/00 ,  H01L25/065 ,  H01L23/48 ,  H01L23/528 ,  H01L23/00 ,  H01L25/00

Abstract: Examples described herein generally relate to multi-chip devices having stacked chips. In an example, a multi-chip device includes a chip stack that includes chips. One or more chips each includes a selection circuit and a broken via pillar that includes first and second continuous portions. The first continuous portion includes a through substrate via and a first metal line. The second continuous portion includes a second metal line. The first and second metal lines are disposed within dielectric layers disposed on a side of the semiconductor substrate of the respective chip. The first and second continuous portions are aligned in a direction normal to the side of the semiconductor substrate. An input node of the selection circuit is connected to one of the first or second metal line. An output node of the selection circuit is connected to the other of the first or second metal line.

公开(公告)号：US11004833B1

公开(公告)日：2021-05-11

申请号：US16792560

申请日：2020-02-17

Applicant: XILINX, INC.

Inventor： Anil Kumar Kandala ,  Vijay Kumar Koganti ,  Santosh Yachareni ,  Sundeep Ram Gopal Agarwal

IPC: H01L25/065 ,  H01L23/48

Abstract: Examples described herein generally relate to multi-chip devices having stacked chips. In an example, a multi-chip device includes a chip stack that includes chips. Neighboring chips are connected to each other. Plural chips of the chips collectively include columns of broken via pillars and bridges. Each of the plural chips has a broken via pillar in each column. The broken via pillar has first and second continuous via pillar portions aligned in a direction normal to a side of a semiconductor substrate of the respective chip. The first continuous via pillar portion is not connected within the broken via pillar to the second continuous via pillar portion. Each of the plural chips has one or more of the bridges. Each bridge connects, within the respective chip, the first continuous via pillar portion in a column and the second continuous via pillar portion in another column.

公开(公告)号：US10886921B1

公开(公告)日：2021-01-05

申请号：US16825340

申请日：2020-03-20

Applicant: XILINX, INC.

Inventor： Vijay Kumar Koganti ,  Anil Kumar Kandala ,  Santosh Yachareni

IPC: G06F7/38 ,  H03K19/177 ,  H03K19/173 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H03K19/20

Abstract: Examples described herein generally relate to multi-chip devices having stacked chips. In an example, a multi-chip device includes a chip stack including a base chip and two or more overlying chips overlying the base chip. Neighboring chips of the chip stack are connected to each other. The chip stack includes identification generation connections and circuits configured to generate a unique identification of each overlying chip based on a relative position of the respective overlying chip with reference to the base chip. The chip stack includes a communication channel from the base chip to each overlying chip. Each overlying chip includes comparison and enable/disable logic (CEDL) communicatively coupled to the communication channel. The CEDL is configured to compare a target identification of data received by the respective overlying chip to the unique identification of the respective overlying chip and responsively enable or disable a recipient circuit of the respective overlying chip.

公开(公告)号：US10069487B1

公开(公告)日：2018-09-04

申请号：US15463824

申请日：2017-03-20

Applicant: Xilinx, Inc.

Inventor： Anil Kumar Kandala ,  Santosh Yachareni ,  Sandeep Vundavalli ,  Vijay Kumar Koganti ,  Golla V S R K Prasad ,  Udaya Kumar Bobbili

IPC: H03H11/26 ,  H03K3/3565 ,  H03K19/173 ,  H03K19/177

Abstract: A disclosed delay circuit includes a plurality of Schmitt triggers that are serially coupled. A first Schmitt trigger of the plurality of Schmitt triggers is configured to receive an input signal. An output control circuit is coupled to receive output signals of two or more Schmitt triggers of the plurality of Schmitt triggers, the output control circuit configured to select a signal from one of the one or more Schmitt triggers as an output signal. The output signal is a delayed version of the input signal.